From ae6dd4b75b96f999e1480287810aef41bbdc4969 Mon Sep 17 00:00:00 2001 From: Xi Ruoyao Date: Tue, 23 Jan 2024 16:00:32 +0000 Subject: [PATCH 049/123] [PATCH v2] gas/NEWS, ld/NEWS: Announce LoongArch changes in 2.42 --- gas/NEWS | 93 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ld/NEWS | 40 ++++++++++++++++++++++++ 2 files changed, 133 insertions(+) diff --git a/gas/NEWS b/gas/NEWS index 59bdd30a..9ad24543 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,98 @@ -*- text -*- +Changes in 2.42: + +* Experimental support in GAS to synthesize CFI for ABI-conformant, + hand-written asm using the new command line option --scfi=experimental on + x86-64. Only System V AMD64 ABI is supported. + +* Add support for the Arm Scalable Vector Extension version 2.1 (SVE2.1) + instructions. + +* Add support for the AArch64 Scalable Matrix Extension version 2.1 (SME2.1) + instructions. + +* Add support for 'armv8.9-a' and 'armv9.4-a' for -march in Arm GAS. + +* Initial support for Intel APX: 32 GPRs, NDD, PUSH2/POP2 and PUSHP/POPP. + +* On RISC-V macro instructions expanding to AUIPC and a load, store, or branch + no longer accept x0 as an intermediate and/or destination register. + +* Add support for Reliability, Availability and Serviceability extension v2 + (RASv2) for AArch64. + +* Add support for 128-bit Atomic Instructions (LSE128) for AArch64. + +* Add support for Guarded Control Stack (GCS) for AArch64. + +* Add support for AArch64 Check Feature Status Extension (CHK). + +* Add support for 'armv8.9-a' and 'armv9.4-a' for -march in AArch64 GAS. + +* Add support for Intel USER_MSR instructions. + +* Add support for Intel AVX10.1. + +* Add support for Intel PBNDKB instructions. + +* Add support for Intel SM4 instructions. + +* Add support for Intel SM3 instructions. + +* Add support for Intel SHA512 instructions. + +* Add support for Intel AVX-VNNI-INT16 instructions. + +* Add support for Cortex-A520 for AArch64. + +* Add support for Cortex-A720 for AArch64. + +* Add support for Cortex-X3 for AArch64. + +* Add support for Cortex-X4 for AArch64. + +* Add support for RISC-V T-Head extensions (XTheadVector, XTheadZvlsseg + and XTheadZvamo) from version 2.3.0 of the T-Head ISA manual. + +* Add support for RISC-V CORE-V extensions (XCVmac, XCValu) with version 1.0. + +* Add support for RISC-V SiFive VCIX extension (XSfVcp) with version 1.0. + +* The BPF assembler now uses semi-colon (;) to separate statements, and + therefore they cannot longer be used to begin line comments. This matches the + behavior of the clang/LLVM BPF assembler. + +* The BPF assembler now allows using both hash (#) and double slash (//) to + begin line comments. + +* Add support for LoongArch v1.10 new instructions: estimated reciprocal + instructions, sub-word atomic instructions, atomic CAS instructions, + 16-byte store-conditional instruction, load-linked instructions with + acquire semantics, and store-conditional instructions with release + semantics. + +* The %call36 relocation operator, along with the pseudo-instructions + call36 and tail36, are now usable with the LoongArch "medium" code + model, allowing text sections up to 128 GiB. + +* TLS descriptors (TLSDESC) are now supported on LoongArch. This includes + the following new relocation operators: %desc_pc_hi20, %desc_pc_lo12, + %desc_ld, and %desc_call, and the la.tls.desc pseudo-instruction. + +* TLS LE relaxation is now supported on LoongArch. New relocation + operators %le_hi20_r, %le_lo12r, and %le_add_r are now available. + +* Add support for LoongArch branch relaxation: a conditional branch with + destination out of its immediate operand range, but still within + a "b"'s range, is now assembled as an inverted branch and a "b". This + works around the unreliable branch offset estimation of the compiler + when .align directive is encoded into a long NOP sequence with an + R_LARCH_RELAX by the assembler. + +* Symbol or label names in LoongArch assembly can now be spelled with + double-quotes. + Changes in 2.41: * Add support for Intel FRED instructions. diff --git a/ld/NEWS b/ld/NEWS index e1ac20b8..687b5190 100644 --- a/ld/NEWS +++ b/ld/NEWS @@ -1,5 +1,45 @@ -*- text -*- +Changes in 2.42: + +* Add -z mark-plt/-z nomark-plt options to x86-64 ELF linker to mark PLT + entries with DT_X86_64_PLT, DT_X86_64_PLTSZ and DT_X86_64_PLTENT dynamic + tags. Also added --enable-mark-plt configure option to mark PLT entries + by default. + +* Support Intel APX relocations. + +* On RISC-V, add ld target option --[no-]check-uleb128. Should rebuild the + objects by binutils 2.42 and up if enabling the option and get warnings, + since the non-zero addend of SUB_ULEB128 shouldn't be generated from .uleb128 + directives. + +* Add support for the KVX instruction set. + +* A new linker script sorting directive has been added: REVERSE. This reverses + the order of the sorting. It may be combined with either SORT_BY_NAME or + SORT_BY_INIT_PRIORITY. + +* Added --warn-execstack-objects to warn about executable stacks only when an + input object file requests one. Also added --error-execstack and + --error-rxw-segments options to convert warnings about executable stacks and + segments into errors. + + Also added --enable-error-execstack=[yes|no] and + --enable-error-rwx-segments=[yes|no] configure options to set the default for + converting warnings into errors. + +* On LoongArch, various linker relaxation bugs are fixed; the most notable + of which is BZ 30944 (incorrect .balign semantics). + +* On LoongArch, the LoongArch ABI v2.30 (LoongArch ELF psABI v20231219) is + now implemented. This includes new relocation types, and changed + semantics for PC-relative relocations handling the higher half of 64-bit + offsets. + +* On LoongArch, link-time TLS optimization and TLS relaxation are now + supported. + Changes in 2.41: * The linker now accepts a command line option of --remap-inputs -- 2.33.0