102 lines
3.7 KiB
Diff
102 lines
3.7 KiB
Diff
From 205e07d68684bc331c16b7bcea44b8d5ca84f7e8 Mon Sep 17 00:00:00 2001
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From: mengqinggang <mengqinggang@loongson.cn>
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Date: Thu, 23 Nov 2023 15:42:49 +0800
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Subject: [PATCH 021/123] LoongArch: Add call36 and tail36 pseudo instructions
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for medium code model
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For tail36, it is necessary to explicitly indicate the temporary register.
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Therefore, the compiler and users will know that the tail will use a register.
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call36 func
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pcalau18i $ra, %call36(func)
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jirl $ra, $ra, 0;
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tail36 $t0, func
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pcalau18i $t0, %call36(func)
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jirl $zero, $t0, 0;
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---
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gas/testsuite/gas/loongarch/medium-call.d | 10 ++++++++--
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gas/testsuite/gas/loongarch/medium-call.s | 2 ++
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ld/testsuite/ld-loongarch-elf/medium-call.s | 2 ++
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opcodes/loongarch-opc.c | 11 +++++++++++
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4 files changed, 23 insertions(+), 2 deletions(-)
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diff --git a/gas/testsuite/gas/loongarch/medium-call.d b/gas/testsuite/gas/loongarch/medium-call.d
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index 4183818c..3491760b 100644
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--- a/gas/testsuite/gas/loongarch/medium-call.d
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+++ b/gas/testsuite/gas/loongarch/medium-call.d
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@@ -10,6 +10,12 @@ Disassembly of section .text:
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[ ]+0:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra, 0
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[ ]+0: R_LARCH_CALL36[ ]+a
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[ ]+4:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0
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-[ ]+8:[ ]+1e00000c[ ]+pcaddu18i[ ]+\$t0, 0
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+[ ]+8:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra, 0
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[ ]+8: R_LARCH_CALL36[ ]+a
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-[ ]+c:[ ]+4c000180[ ]+jr[ ]+\$t0
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+[ ]+c:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0
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+[ ]+10:[ ]+1e00000c[ ]+pcaddu18i[ ]+\$t0, 0
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+[ ]+10: R_LARCH_CALL36[ ]+a
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+[ ]+14:[ ]+4c000180[ ]+jr[ ]+\$t0
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+[ ]+18:[ ]+1e00000c[ ]+pcaddu18i[ ]+\$t0, 0
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+[ ]+18: R_LARCH_CALL36[ ]+a
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+[ ]+1c:[ ]+4c000180[ ]+jr[ ]+\$t0
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diff --git a/gas/testsuite/gas/loongarch/medium-call.s b/gas/testsuite/gas/loongarch/medium-call.s
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index f2977d1c..74d15076 100644
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--- a/gas/testsuite/gas/loongarch/medium-call.s
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+++ b/gas/testsuite/gas/loongarch/medium-call.s
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@@ -1,6 +1,8 @@
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# call .L1, r1(ra) temp register, r1(ra) return register.
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+ call36 a
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pcaddu18i $r1, %call36(a)
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jirl $r1, $r1, 0
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# tail .L1, r12(t0) temp register, r0(zero) return register.
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+ tail36 $r12, a
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pcaddu18i $r12, %call36(a)
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jirl $r0, $r12, 0
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diff --git a/ld/testsuite/ld-loongarch-elf/medium-call.s b/ld/testsuite/ld-loongarch-elf/medium-call.s
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index 4d1888b7..50a6b8e7 100644
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--- a/ld/testsuite/ld-loongarch-elf/medium-call.s
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+++ b/ld/testsuite/ld-loongarch-elf/medium-call.s
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@@ -1,7 +1,9 @@
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.L1:
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# call .L1, r1(ra) temp register, r1(ra) return register.
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+ call36 .L1
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pcaddu18i $r1, %call36(.L1)
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jirl $r1, $r1, 0
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# tail .L1, r12(t0) temp register, r0(zero) return register.
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+ tail36 $r12, .L1
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pcaddu18i $r12, %call36(.L1)
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jirl $r0, $r12, 0
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diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
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index 15c7da63..b47817f8 100644
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--- a/opcodes/loongarch-opc.c
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+++ b/opcodes/loongarch-opc.c
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@@ -293,6 +293,15 @@ const char *const loongarch_x_normal_name[32] =
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&LARCH_opts.ase_lp64, \
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&LARCH_opts.ase_gpcr
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+#define INSN_LA_CALL \
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+ "pcaddu18i $ra,%%call36(%1);" \
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+ "jirl $ra,$ra,0;", \
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+ 0, 0
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+
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+#define INSN_LA_TAIL \
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+ "pcaddu18i %1,%%call36(%2);" \
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+ "jirl $zero,%1,0;", \
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+ 0, 0
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static struct loongarch_opcode loongarch_macro_opcodes[] =
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{
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@@ -340,6 +349,8 @@ static struct loongarch_opcode loongarch_macro_opcodes[] =
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{ 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64, 0 },
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{ 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64_LARGE_ABS, 0 },
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{ 0, 0, "la.tls.gd", "r,r,l", INSN_LA_TLS_GD64_LARGE_PCREL, 0 },
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+ { 0, 0, "call36", "la", INSN_LA_CALL, 0 },
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+ { 0, 0, "tail36", "r,la", INSN_LA_TAIL, 0 },
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{ 0, 0, "pcaddi", "r,la", "pcaddi %1, %%pcrel_20(%2)", &LARCH_opts.ase_ilp32, 0, 0 },
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{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
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};
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--
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2.33.0
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