e782454207
Sync some patchs from upstreaming, includind some bugfixes, hns3 pmd flow rule priority feature, hns3 pmd outer VLAN flow match feature, and support dump reigser names and filter. This patch set is modified as follows: - net/hns3: fix cannot fully use hardware flow director table - net/hns3: fix error code for repeatedly create counter - net/hns3: support flow rule priority - common/nfp: use new kvargs process API - net/tap: use new kvargs process API - net/sfc: use new kvargs process API - kvargs: rework process API - net/hns3: fix variable type - net/hns3: fix pointer offset - net/hns3: fix error log - net/hns3: support filtering registers by module names - net/hns3: support reporting names of registers - net/hns3: refactor register dump - net/hns3: remove separators between register module - net/hns3: fix dump counter of registers - net/hns3: remove some basic address dump - telemetry: register command with private argument - ethdev: fix race on ports in telemetry endpoints - ethdev: add telemetry command for registers - ethdev: add report of register names and filter - net/hns3: support outer VLAN flow match - net/hns3: register VLAN flow match mode parameter - net/hns3: support general tunnel flow match - net/hns3: restrict tunnel flow rule to one header - net/hns3: remove ROH devices - net/hns3: dump queue head and tail pointer info - dmadev: fix potential null pointer access - net/hns3: verify reset type from firmware - ethdev: verify queue ID in Tx done cleanup Signed-off-by: Dengdui Huang <huangdengdui@huawei.com> (cherry picked from commit a1c828e1eb9cf716187d2a7656023e95bdce9b55)
276 lines
7.4 KiB
Diff
276 lines
7.4 KiB
Diff
From f1948283fb0d54c33db64897382d0c7c0d29eedc Mon Sep 17 00:00:00 2001
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From: Jie Hai <haijie1@huawei.com>
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Date: Thu, 26 Sep 2024 20:42:47 +0800
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Subject: [PATCH] net/hns3: refactor register dump
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[ upstream commit 8cdddc252dd5320bbbb1df948bbdd8d19f8fda22 ]
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This patch refactors codes dumping registers from firmware.
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Signed-off-by: Jie Hai <haijie1@huawei.com>
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Acked-by: Chengwen Feng <fengchengwen@huawei.com>
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---
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drivers/net/hns3/hns3_regs.c | 203 ++++++++++++++++++++---------------
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1 file changed, 115 insertions(+), 88 deletions(-)
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diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c
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index c8e3fb1..c7dadbe 100644
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--- a/drivers/net/hns3/hns3_regs.c
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+++ b/drivers/net/hns3/hns3_regs.c
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@@ -104,12 +104,93 @@ hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit,
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return 0;
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}
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+static int
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+hns3_get_32_64_regs_cnt(struct hns3_hw *hw, uint32_t *count)
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+{
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+ uint32_t regs_num_32_bit, regs_num_64_bit;
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+ int ret;
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+
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+ ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit);
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+ if (ret) {
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+ hns3_err(hw, "fail to get the number of registers, "
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+ "ret = %d.", ret);
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+ return ret;
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+ }
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+
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+ *count += regs_num_32_bit + regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE;
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+ return 0;
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+}
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+
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+static int
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+hns3_get_dfx_reg_bd_num(struct hns3_hw *hw, uint32_t *bd_num_list,
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+ uint32_t list_size)
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+{
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+#define HNS3_GET_DFX_REG_BD_NUM_SIZE 4
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+ struct hns3_cmd_desc desc[HNS3_GET_DFX_REG_BD_NUM_SIZE];
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+ uint32_t index, desc_index;
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+ uint32_t bd_num;
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+ uint32_t i;
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+ int ret;
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+
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+ for (i = 0; i < HNS3_GET_DFX_REG_BD_NUM_SIZE - 1; i++) {
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+ hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_DFX_BD_NUM, true);
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+ desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
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+ }
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+ /* The last BD does not need a next flag */
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+ hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_DFX_BD_NUM, true);
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+
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+ ret = hns3_cmd_send(hw, desc, HNS3_GET_DFX_REG_BD_NUM_SIZE);
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+ if (ret) {
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+ hns3_err(hw, "fail to get dfx bd num, ret = %d.", ret);
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+ return ret;
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+ }
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+
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+ /* The first data in the first BD is a reserved field */
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+ for (i = 1; i <= list_size; i++) {
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+ desc_index = i / HNS3_CMD_DESC_DATA_NUM;
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+ index = i % HNS3_CMD_DESC_DATA_NUM;
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+ bd_num = rte_le_to_cpu_32(desc[desc_index].data[index]);
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+ bd_num_list[i - 1] = bd_num;
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+ }
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+
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+ return 0;
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+}
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+
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+static int
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+hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count)
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+{
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+ int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list);
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+ uint32_t bd_num_list[opcode_num];
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+ int ret;
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+ int i;
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+
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+ ret = hns3_get_dfx_reg_bd_num(hw, bd_num_list, opcode_num);
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+ if (ret)
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+ return ret;
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+
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+ for (i = 0; i < opcode_num; i++)
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+ *count += bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM;
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+
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+ return 0;
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+}
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+
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+static int
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+hns3_get_firmware_reg_cnt(struct hns3_hw *hw, uint32_t *count)
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+{
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+ int ret;
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+
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+ ret = hns3_get_32_64_regs_cnt(hw, count);
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+ if (ret < 0)
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+ return ret;
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+
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+ return hns3_get_dfx_reg_cnt(hw, count);
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+}
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+
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static int
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hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length)
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{
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struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
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- uint32_t regs_num_32_bit, regs_num_64_bit;
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- uint32_t dfx_reg_cnt;
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+ uint32_t dfx_reg_cnt = 0;
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uint32_t common_cnt;
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uint32_t len;
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int ret;
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@@ -125,16 +206,7 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length)
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len /= sizeof(uint32_t);
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if (!hns->is_vf) {
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- ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit);
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- if (ret) {
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- hns3_err(hw, "fail to get the number of registers, "
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- "ret = %d.", ret);
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- return ret;
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- }
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- dfx_reg_cnt = regs_num_32_bit +
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- regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE;
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-
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- ret = hns3_get_dfx_reg_cnt(hw, &dfx_reg_cnt);
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+ ret = hns3_get_firmware_reg_cnt(hw, &dfx_reg_cnt);
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if (ret) {
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hns3_err(hw, "fail to get the number of dfx registers, "
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"ret = %d.", ret);
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@@ -304,41 +376,6 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data)
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return data - origin_data_ptr;
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}
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-static int
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-hns3_get_dfx_reg_bd_num(struct hns3_hw *hw, uint32_t *bd_num_list,
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- uint32_t list_size)
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-{
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-#define HNS3_GET_DFX_REG_BD_NUM_SIZE 4
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- struct hns3_cmd_desc desc[HNS3_GET_DFX_REG_BD_NUM_SIZE];
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- uint32_t index, desc_index;
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- uint32_t bd_num;
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- uint32_t i;
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- int ret;
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-
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- for (i = 0; i < HNS3_GET_DFX_REG_BD_NUM_SIZE - 1; i++) {
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- hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_DFX_BD_NUM, true);
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- desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
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- }
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- /* The last BD does not need a next flag */
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- hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_DFX_BD_NUM, true);
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-
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- ret = hns3_cmd_send(hw, desc, HNS3_GET_DFX_REG_BD_NUM_SIZE);
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- if (ret) {
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- hns3_err(hw, "fail to get dfx bd num, ret = %d.\n", ret);
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- return ret;
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- }
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-
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- /* The first data in the first BD is a reserved field */
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- for (i = 1; i <= list_size; i++) {
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- desc_index = i / HNS3_CMD_DESC_DATA_NUM;
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- index = i % HNS3_CMD_DESC_DATA_NUM;
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- bd_num = rte_le_to_cpu_32(desc[desc_index].data[index]);
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- bd_num_list[i - 1] = bd_num;
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- }
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-
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- return 0;
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-}
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-
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static int
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hns3_dfx_reg_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc,
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int bd_num, uint32_t opcode)
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@@ -379,24 +416,6 @@ hns3_dfx_reg_fetch_data(struct hns3_cmd_desc *desc, int bd_num, uint32_t *reg)
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return reg_num;
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}
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-static int
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-hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count)
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-{
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- int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list);
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- uint32_t bd_num_list[opcode_num];
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- int ret;
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- int i;
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-
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- ret = hns3_get_dfx_reg_bd_num(hw, bd_num_list, opcode_num);
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- if (ret)
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- return ret;
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-
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- for (i = 0; i < opcode_num; i++)
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- *count += bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM;
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-
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- return 0;
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-}
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-
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static int
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hns3_get_dfx_regs(struct hns3_hw *hw, void **data)
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{
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@@ -436,13 +455,41 @@ hns3_get_dfx_regs(struct hns3_hw *hw, void **data)
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return ret;
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}
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+static int
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+hns3_get_regs_from_firmware(struct hns3_hw *hw, uint32_t *data)
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+{
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+ uint32_t regs_num_32_bit;
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+ uint32_t regs_num_64_bit;
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+ int ret;
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+
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+ ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit);
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+ if (ret) {
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+ hns3_err(hw, "Get register number failed, ret = %d", ret);
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+ return ret;
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+ }
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+
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+ ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data);
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+ if (ret) {
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+ hns3_err(hw, "Get 32 bit register failed, ret = %d", ret);
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+ return ret;
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+ }
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+ data += regs_num_32_bit;
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+
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+ ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data);
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+ if (ret) {
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+ hns3_err(hw, "Get 64 bit register failed, ret = %d", ret);
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+ return ret;
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+ }
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+ data += regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE;
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+
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+ return hns3_get_dfx_regs(hw, (void **)&data);
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+}
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+
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int
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hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)
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{
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struct hns3_adapter *hns = eth_dev->data->dev_private;
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struct hns3_hw *hw = &hns->hw;
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- uint32_t regs_num_32_bit;
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- uint32_t regs_num_64_bit;
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uint32_t length;
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uint32_t *data;
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int ret;
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@@ -470,26 +517,6 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)
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if (hns->is_vf)
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return 0;
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- ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit);
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- if (ret) {
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- hns3_err(hw, "Get register number failed, ret = %d", ret);
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- return ret;
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- }
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-
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/* fetching PF common registers values from firmware */
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- ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data);
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- if (ret) {
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- hns3_err(hw, "Get 32 bit register failed, ret = %d", ret);
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- return ret;
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- }
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- data += regs_num_32_bit;
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-
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- ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data);
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- if (ret) {
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- hns3_err(hw, "Get 64 bit register failed, ret = %d", ret);
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- return ret;
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- }
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- data += regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE;
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-
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- return hns3_get_dfx_regs(hw, (void **)&data);
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+ return hns3_get_regs_from_firmware(hw, data);
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}
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--
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2.33.0
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