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dpdk/0065-net-hns3-support-filtering-registers-by-module-names.patch
Dengdui Huang e782454207 sync some patchs from upstreaming 
Sync some patchs from upstreaming, includind some bugfixes, hns3 pmd
flow rule priority feature, hns3 pmd outer VLAN flow match feature,
and support dump reigser names and filter.
This patch set is modified as follows:
- net/hns3: fix cannot fully use hardware flow director table
- net/hns3: fix error code for repeatedly create counter
- net/hns3: support flow rule priority
- common/nfp: use new kvargs process API
- net/tap: use new kvargs process API
- net/sfc: use new kvargs process API
- kvargs: rework process API
- net/hns3: fix variable type
- net/hns3: fix pointer offset
- net/hns3: fix error log
- net/hns3: support filtering registers by module names
- net/hns3: support reporting names of registers
- net/hns3: refactor register dump
- net/hns3: remove separators between register module
- net/hns3: fix dump counter of registers
- net/hns3: remove some basic address dump
- telemetry: register command with private argument
- ethdev: fix race on ports in telemetry endpoints
- ethdev: add telemetry command for registers
- ethdev: add report of register names and filter
- net/hns3: support outer VLAN flow match
- net/hns3: register VLAN flow match mode parameter
- net/hns3: support general tunnel flow match
- net/hns3: restrict tunnel flow rule to one header
- net/hns3: remove ROH devices
- net/hns3: dump queue head and tail pointer info
- dmadev: fix potential null pointer access
- net/hns3: verify reset type from firmware
- ethdev: verify queue ID in Tx done cleanup

Signed-off-by: Dengdui Huang <huangdengdui@huawei.com>
(cherry picked from commit a1c828e1eb9cf716187d2a7656023e95bdce9b55)
2024-11-22 10:06:08 +08:00

441 lines
14 KiB
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From 9b47034619f1905f6e54d27d11606ad503115625 Mon Sep 17 00:00:00 2001
From: Jie Hai <haijie1@huawei.com>
Date: Thu, 26 Sep 2024 20:42:49 +0800
Subject: [PATCH] net/hns3: support filtering registers by module names
[ upstream commit 99d3bd8b85d357c8d4e7ee23765a073f4970ff74 ]
This patch support dumping registers which module name is the
`filter` string. The module names are in lower case and so is
the `filter`. Available module names are cmdq, common_pf,
common_vf, ring, tqp_intr, 32_bit_dfx, 64_bit_dfx, bios, igu_egu,
ssu, ppp, rpu, ncsi, rtc, rcb, etc.
Signed-off-by: Jie Hai <haijie1@huawei.com>
Acked-by: Chengwen Feng <fengchengwen@huawei.com>
---
doc/guides/nics/hns3.rst | 9 ++
drivers/net/hns3/hns3_regs.c | 257 ++++++++++++++++++++---------------
2 files changed, 159 insertions(+), 107 deletions(-)
diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst
index 4f0bc42..bdc10da 100644
--- a/doc/guides/nics/hns3.rst
+++ b/doc/guides/nics/hns3.rst
@@ -417,6 +417,15 @@ be provided to avoid scheduling the CPU core used by DPDK application threads fo
other tasks. Before starting the Linux OS, add the kernel isolation boot parameter.
For example, "isolcpus=1-18 nohz_full=1-18 rcu_nocbs=1-18".
+Dump registers
+--------------
+
+HNS3 supports dumping registers values with their names,
+and supports filtering by module names.
+The available module names are ``bios``, ``ssu``, ``igu_egu``,
+``rpu``, ``ncsi``, ``rtc``, ``ppp``, ``rcb``, ``tqp``, ``rtc``, ``cmdq``,
+``common_pf``, ``common_vf``, ``ring``, ``tqp_intr``, ``32_bit_dfx``,
+``64_bit_dfx``.
Limitations or Known issues
---------------------------
diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c
index 22151dd..8148a63 100644
--- a/drivers/net/hns3/hns3_regs.c
+++ b/drivers/net/hns3/hns3_regs.c
@@ -12,7 +12,7 @@
#define HNS3_64_BIT_REG_OUTPUT_SIZE (sizeof(uint64_t) / sizeof(uint32_t))
-static int hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count);
+#define HNS3_MAX_MODULES_LEN 512
struct hns3_dirt_reg_entry {
const char *name;
@@ -795,11 +795,39 @@ enum hns3_reg_modules {
HNS3_64_BIT_DFX,
};
+#define HNS3_MODULE_MASK(x) RTE_BIT32(x)
+#define HNS3_VF_MODULES (HNS3_MODULE_MASK(HNS3_CMDQ) | HNS3_MODULE_MASK(HNS3_COMMON_VF) | \
+ HNS3_MODULE_MASK(HNS3_RING) | HNS3_MODULE_MASK(HNS3_TQP_INTR))
+#define HNS3_VF_ONLY_MODULES HNS3_MODULE_MASK(HNS3_COMMON_VF)
+
struct hns3_reg_list {
const void *reg_list;
uint32_t entry_num;
};
+struct {
+ const char *name;
+ uint32_t module;
+} hns3_module_name_map[] = {
+ { "bios", HNS3_MODULE_MASK(HNS3_BIOS_COMMON) },
+ { "ssu", HNS3_MODULE_MASK(HNS3_SSU_0) | HNS3_MODULE_MASK(HNS3_SSU_1) |
+ HNS3_MODULE_MASK(HNS3_SSU_2) },
+ { "igu_egu", HNS3_MODULE_MASK(HNS3_IGU_EGU) },
+ { "rpu", HNS3_MODULE_MASK(HNS3_RPU_0) | HNS3_MODULE_MASK(HNS3_RPU_1) },
+ { "ncsi", HNS3_MODULE_MASK(HNS3_NCSI) },
+ { "rtc", HNS3_MODULE_MASK(HNS3_RTC) },
+ { "ppp", HNS3_MODULE_MASK(HNS3_PPP) },
+ { "rcb", HNS3_MODULE_MASK(HNS3_RCB) },
+ { "tqp", HNS3_MODULE_MASK(HNS3_TQP) },
+ { "cmdq", HNS3_MODULE_MASK(HNS3_CMDQ) },
+ { "common_pf", HNS3_MODULE_MASK(HNS3_COMMON_PF) },
+ { "common_vf", HNS3_MODULE_MASK(HNS3_COMMON_VF) },
+ { "ring", HNS3_MODULE_MASK(HNS3_RING) },
+ { "tqp_intr", HNS3_MODULE_MASK(HNS3_TQP_INTR) },
+ { "32_bit_dfx", HNS3_MODULE_MASK(HNS3_32_BIT_DFX) },
+ { "64_bit_dfx", HNS3_MODULE_MASK(HNS3_64_BIT_DFX) },
+};
+
static struct hns3_reg_list hns3_reg_lists[] = {
[HNS3_BIOS_COMMON] = { dfx_bios_common_reg_list, RTE_DIM(dfx_bios_common_reg_list) },
[HNS3_SSU_0] = { dfx_ssu_reg_0_list, RTE_DIM(dfx_ssu_reg_0_list) },
@@ -863,21 +891,58 @@ hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit,
return 0;
}
-static int
-hns3_get_32_64_regs_cnt(struct hns3_hw *hw, uint32_t *count)
+static const char *
+hns3_get_name_by_module(enum hns3_reg_modules module)
{
- uint32_t regs_num_32_bit, regs_num_64_bit;
- int ret;
+ size_t i;
- ret = hns3_get_regs_num(hw, &regs_num_32_bit, &regs_num_64_bit);
- if (ret) {
- hns3_err(hw, "fail to get the number of registers, "
- "ret = %d.", ret);
- return ret;
+ for (i = 0; i < RTE_DIM(hns3_module_name_map); i++) {
+ if (hns3_module_name_map[i].module && HNS3_MODULE_MASK(module) != 0)
+ return hns3_module_name_map[i].name;
}
+ return "unknown";
+}
- *count += regs_num_32_bit + regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE;
- return 0;
+static void
+hns3_get_module_names(char *names, uint32_t len)
+{
+ size_t i;
+
+ for (i = 0; i < RTE_DIM(hns3_module_name_map); i++) {
+ strlcat(names, " ", len);
+ strlcat(names, hns3_module_name_map[i].name, len);
+ }
+}
+
+static uint32_t
+hns3_parse_modules_by_filter(struct hns3_hw *hw, const char *filter)
+{
+ struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
+ char names[HNS3_MAX_MODULES_LEN] = {0};
+ uint32_t modules = 0;
+ size_t i;
+
+ if (filter == NULL) {
+ modules = (1 << RTE_DIM(hns3_reg_lists)) - 1;
+ } else {
+ for (i = 0; i < RTE_DIM(hns3_module_name_map); i++) {
+ if (strcmp(filter, hns3_module_name_map[i].name) == 0) {
+ modules |= hns3_module_name_map[i].module;
+ break;
+ }
+ }
+ }
+
+ if (hns->is_vf)
+ modules &= HNS3_VF_MODULES;
+ else
+ modules &= ~HNS3_VF_ONLY_MODULES;
+ if (modules == 0) {
+ hns3_get_module_names(names, HNS3_MAX_MODULES_LEN);
+ hns3_err(hw, "mismatched module name! Available names are:%s.",
+ names);
+ }
+ return modules;
}
static int
@@ -915,73 +980,25 @@ hns3_get_dfx_reg_bd_num(struct hns3_hw *hw, uint32_t *bd_num_list,
return 0;
}
-static int
-hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count)
-{
- int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list);
- uint32_t bd_num_list[opcode_num];
- uint32_t reg_num;
- int ret;
- int i;
-
- ret = hns3_get_dfx_reg_bd_num(hw, bd_num_list, opcode_num);
- if (ret)
- return ret;
-
- for (i = 0; i < opcode_num; i++) {
- reg_num = bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM;
- if (reg_num != hns3_reg_lists[i].entry_num) {
- hns3_err(hw, "Query register number differ from the list!");
- return -EINVAL;
- }
- *count += reg_num;
- }
-
- return 0;
-}
-
-static int
-hns3_get_firmware_reg_cnt(struct hns3_hw *hw, uint32_t *count)
-{
- int ret;
-
- ret = hns3_get_32_64_regs_cnt(hw, count);
- if (ret < 0)
- return ret;
-
- return hns3_get_dfx_reg_cnt(hw, count);
-}
-
-static int
-hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length)
+static uint32_t
+hns3_get_regs_length(struct hns3_hw *hw, uint32_t modules)
{
- struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
- uint32_t dfx_reg_cnt = 0;
- uint32_t common_cnt;
- uint32_t len;
- int ret;
-
- if (hns->is_vf)
- common_cnt = RTE_DIM(common_vf_reg_list);
- else
- common_cnt = RTE_DIM(common_reg_list);
+ uint32_t reg_num = 0, length = 0;
+ uint32_t i;
- len = RTE_DIM(cmdq_reg_list) + common_cnt +
- RTE_DIM(ring_reg_list) * hw->tqps_num +
- RTE_DIM(tqp_intr_reg_list) * hw->intr_tqps_num;
+ for (i = 0; i < RTE_DIM(hns3_reg_lists); i++) {
+ if ((RTE_BIT32(i) & modules) == 0)
+ continue;
+ reg_num = hns3_reg_lists[i].entry_num;
+ if (i == HNS3_RING)
+ reg_num *= hw->tqps_num;
+ else if (i == HNS3_TQP_INTR)
+ reg_num *= hw->intr_tqps_num;
- if (!hns->is_vf) {
- ret = hns3_get_firmware_reg_cnt(hw, &dfx_reg_cnt);
- if (ret) {
- hns3_err(hw, "fail to get the number of dfx registers, "
- "ret = %d.", ret);
- return ret;
- }
- len += dfx_reg_cnt;
+ length += reg_num;
}
- *length = len;
- return 0;
+ return length;
}
static void
@@ -1122,12 +1139,15 @@ hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, struct rte_dev_reg_i
static void
hns3_direct_access_regs_help(struct hns3_hw *hw, struct rte_dev_reg_info *regs,
- enum hns3_reg_modules idx)
+ uint32_t modules, enum hns3_reg_modules idx)
{
const struct hns3_dirt_reg_entry *reg_list;
uint32_t *data = regs->data;
size_t reg_num, i, cnt;
+ if ((modules & HNS3_MODULE_MASK(idx)) == 0)
+ return;
+
data += regs->length;
reg_num = hns3_reg_lists[idx].entry_num;
reg_list = hns3_reg_lists[idx].reg_list;
@@ -1155,14 +1175,14 @@ hns3_get_module_tqp_reg_offset(enum hns3_reg_modules idx, uint16_t queue_id)
static void
hns3_direct_access_tqp_regs_help(struct hns3_hw *hw, struct rte_dev_reg_info *regs,
- enum hns3_reg_modules idx)
+ uint32_t modules, enum hns3_reg_modules idx)
{
const struct hns3_dirt_reg_entry *reg_list;
uint16_t tqp_num, reg_offset;
uint32_t *data = regs->data;
uint32_t reg_num, i, j;
- if (idx != HNS3_RING && idx != HNS3_TQP_INTR)
+ if ((modules & HNS3_MODULE_MASK(idx)) == 0)
return;
tqp_num = (idx == HNS3_RING) ? hw->tqps_num : hw->intr_tqps_num;
@@ -1182,18 +1202,13 @@ hns3_direct_access_tqp_regs_help(struct hns3_hw *hw, struct rte_dev_reg_info *re
}
static void
-hns3_direct_access_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs)
+hns3_direct_access_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs, uint32_t modules)
{
- struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
-
- if (hns->is_vf)
- hns3_direct_access_regs_help(hw, regs, HNS3_COMMON_VF);
- else
- hns3_direct_access_regs_help(hw, regs, HNS3_COMMON_PF);
-
- hns3_direct_access_regs_help(hw, regs, HNS3_CMDQ);
- hns3_direct_access_tqp_regs_help(hw, regs, HNS3_RING);
- hns3_direct_access_tqp_regs_help(hw, regs, HNS3_TQP_INTR);
+ hns3_direct_access_regs_help(hw, regs, modules, HNS3_COMMON_VF);
+ hns3_direct_access_regs_help(hw, regs, modules, HNS3_COMMON_PF);
+ hns3_direct_access_regs_help(hw, regs, modules, HNS3_CMDQ);
+ hns3_direct_access_tqp_regs_help(hw, regs, modules, HNS3_RING);
+ hns3_direct_access_tqp_regs_help(hw, regs, modules, HNS3_TQP_INTR);
}
static int
@@ -1237,7 +1252,7 @@ hns3_dfx_reg_fetch_data(struct hns3_cmd_desc *desc, int bd_num, uint32_t *reg)
}
static int
-hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs)
+hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs, uint32_t modules)
{
int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list);
uint32_t max_bd_num, bd_num, opcode, regs_num;
@@ -1262,6 +1277,8 @@ hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs)
for (i = 0; i < opcode_num; i++) {
opcode = hns3_dfx_reg_opcode_list[i];
bd_num = bd_num_list[i];
+ if ((modules & HNS3_MODULE_MASK(i)) == 0)
+ continue;
if (bd_num == 0)
continue;
ret = hns3_dfx_reg_cmd_send(hw, cmd_descs, bd_num, opcode);
@@ -1270,6 +1287,11 @@ hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs)
data += regs->length;
regs_num = hns3_dfx_reg_fetch_data(cmd_descs, bd_num, data);
+ if (regs_num != hns3_reg_lists[i].entry_num) {
+ hns3_err(hw, "Query register number differ from the list for module %s!",
+ hns3_get_name_by_module(i));
+ return -EINVAL;
+ }
hns3_fill_dfx_regs_name(hw, regs, hns3_reg_lists[i].reg_list, regs_num);
regs->length += regs_num;
}
@@ -1279,14 +1301,14 @@ hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs)
}
static int
-hns3_get_regs_from_firmware(struct hns3_hw *hw, struct rte_dev_reg_info *regs)
+hns3_get_32_b4_bit_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs, uint32_t modules)
{
- struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
uint32_t regs_num_32_bit;
uint32_t regs_num_64_bit;
int ret;
- if (hns->is_vf)
+ if ((modules & HNS3_MODULE_MASK(HNS3_32_BIT_DFX)) == 0 &&
+ (modules & HNS3_MODULE_MASK(HNS3_64_BIT_DFX)) == 0)
return 0;
ret = hns3_get_regs_num(hw, &regs_num_32_bit, &regs_num_64_bit);
@@ -1295,19 +1317,39 @@ hns3_get_regs_from_firmware(struct hns3_hw *hw, struct rte_dev_reg_info *regs)
return ret;
}
- ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, regs);
- if (ret) {
- hns3_err(hw, "Get 32 bit register failed, ret = %d", ret);
- return ret;
+ if ((modules & HNS3_MODULE_MASK(HNS3_32_BIT_DFX)) != 0) {
+ ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, regs);
+ if (ret) {
+ hns3_err(hw, "Get 32 bit register failed, ret = %d", ret);
+ return ret;
+ }
}
- ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, regs);
- if (ret) {
- hns3_err(hw, "Get 64 bit register failed, ret = %d", ret);
- return ret;
+ if ((modules & HNS3_MODULE_MASK(HNS3_64_BIT_DFX)) != 0) {
+ ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, regs);
+ if (ret) {
+ hns3_err(hw, "Get 64 bit register failed, ret = %d", ret);
+ return ret;
+ }
}
- return hns3_get_dfx_regs(hw, regs);
+ return 0;
+}
+
+static int
+hns3_get_regs_from_firmware(struct hns3_hw *hw, struct rte_dev_reg_info *regs, uint32_t modules)
+{
+ struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
+ int ret;
+
+ if (hns->is_vf)
+ return 0;
+
+ ret = hns3_get_32_b4_bit_regs(hw, regs, modules);
+ if (ret != 0)
+ return ret;
+
+ return hns3_get_dfx_regs(hw, regs, modules);
}
int
@@ -1315,13 +1357,14 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)
{
struct hns3_adapter *hns = eth_dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
+ uint32_t modules;
uint32_t length;
- int ret;
- ret = hns3_get_regs_length(hw, &length);
- if (ret)
- return ret;
+ modules = hns3_parse_modules_by_filter(hw, regs->filter);
+ if (modules == 0)
+ return -EINVAL;
+ length = hns3_get_regs_length(hw, modules);
if (regs->data == NULL) {
regs->length = length;
regs->width = sizeof(uint32_t);
@@ -1337,8 +1380,8 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)
regs->length = 0;
/* fetching per-PF registers values from PF PCIe register space */
- hns3_direct_access_regs(hw, regs);
+ hns3_direct_access_regs(hw, regs, modules);
/* fetching PF common registers values from firmware */
- return hns3_get_regs_from_firmware(hw, regs);
+ return hns3_get_regs_from_firmware(hw, regs, modules);
}
--
2.33.0
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