365 lines
11 KiB
Diff
365 lines
11 KiB
Diff
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From 637e6e0c2f3a38ba9f56174e2e92a3ff39e88344 Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Sat, 20 Jul 2024 20:38:13 +0800
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Subject: [PATCH 10/20] LoongArch: Expand some SImode operations through
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"si3_extend" instructions if TARGET_64BIT
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We already had "si3_extend" insns and we hoped the fwprop or combine
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passes can use them to remove unnecessary sign extensions. But this
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does not always work: for cases like x << 1 | y, the compiler
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tends to do
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(sign_extend:DI
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(ior:SI (ashift:SI (reg:SI $r4)
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(const_int 1))
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(reg:SI $r5)))
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instead of
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(ior:DI (sign_extend:DI (ashift:SI (reg:SI $r4) (const_int 1)))
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(sign_extend:DI (reg:SI $r5)))
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So we cannot match the ashlsi3_extend instruction here and we get:
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slli.w $r4,$r4,1
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or $r4,$r5,$r4
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slli.w $r4,$r4,0 # <= redundant
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jr $r1
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To eliminate this redundant extension we need to turn SImode shift etc.
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to DImode "si3_extend" operations earlier, when we expand the SImode
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operation. We are already doing this for addition, now do it for
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shifts, rotates, substract, multiplication, division, and modulo as
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well.
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The bytepick.w definition for TARGET_64BIT needs to be adjusted so it
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won't be undone by the shift expanding.
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gcc/ChangeLog:
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* config/loongarch/loongarch.md (optab): Add (rotatert "rotr").
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(<optab:any_shift><mode>3, <optab:any_div><mode>3,
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sub<mode>3, rotr<mode>3, mul<mode>3): Add a "*" to the insn name
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so we can redefine the names with define_expand.
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(*<optab:any_shift>si3_extend): Remove "*" so we can use them
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in expanders.
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(*subsi3_extended, *mulsi3_extended): Likewise, also remove the
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trailing "ed" for consistency.
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(*<optab:any_div>si3_extended): Add mode for sign_extend to
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prevent an ICE using it in expanders.
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(shift_w, arith_w): New define_code_iterator.
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(<optab:any_w><mode>3): New define_expand. Expand with
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<optab:any_w>si3_extend for SImode if TARGET_64BIT.
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(<optab:arith_w><mode>3): Likewise.
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(mul<mode>3): Expand to mulsi3_extended for SImode if
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TARGET_64BIT and ISA_HAS_DIV32.
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(<optab:any_div><mode>3): Expand to <optab:any_div>si3_extended
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for SImode if TARGET_64BIT.
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(rotl<mode>3): Expand to rotrsi3_extend for SImode if
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TARGET_64BIT.
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(bytepick_w_<bytepick_imm>): Add mode for lshiftrt and ashift.
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(bitsize, bytepick_imm, bytepick_w_ashift_amount): New
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define_mode_attr.
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(bytepick_w_<bytepick_imm>_extend): Adjust for the RTL change
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caused by 32-bit shift expanding. Now bytepick_imm only covers
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2 and 3, separate one remaining case to ...
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(bytepick_w_1_extend): ... here, new define_insn.
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gcc/testsuite/ChangeLog:
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* gcc.target/loongarch/bitwise_extend.c: New test.
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---
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gcc/config/loongarch/loongarch.md | 131 +++++++++++++++---
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.../gcc.target/loongarch/bitwise_extend.c | 45 ++++++
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2 files changed, 154 insertions(+), 22 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/loongarch/bitwise_extend.c
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diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
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index 459ad30b9..9bad79bbf 100644
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--- a/gcc/config/loongarch/loongarch.md
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+++ b/gcc/config/loongarch/loongarch.md
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@@ -546,6 +546,7 @@
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(define_code_attr optab [(ashift "ashl")
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(ashiftrt "ashr")
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(lshiftrt "lshr")
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+ (rotatert "rotr")
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(ior "ior")
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(xor "xor")
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(and "and")
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@@ -624,6 +625,49 @@
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(48 "6")
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(56 "7")])
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+;; Expand some 32-bit operations to si3_extend operations if TARGET_64BIT
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+;; so the redundant sign extension can be removed if the output is used as
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+;; an input of a bitwise operation. Note plus, rotl, and div are handled
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+;; separately.
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+(define_code_iterator shift_w [any_shift rotatert])
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+(define_code_iterator arith_w [minus mult])
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+
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+(define_expand "<optab><mode>3"
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+ [(set (match_operand:GPR 0 "register_operand" "=r")
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+ (shift_w:GPR (match_operand:GPR 1 "register_operand" "r")
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+ (match_operand:SI 2 "arith_operand" "rI")))]
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+ ""
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+{
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+ if (TARGET_64BIT && <MODE>mode == SImode)
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+ {
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+ rtx t = gen_reg_rtx (DImode);
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+ emit_insn (gen_<optab>si3_extend (t, operands[1], operands[2]));
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+ t = gen_lowpart (SImode, t);
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+ SUBREG_PROMOTED_VAR_P (t) = 1;
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+ SUBREG_PROMOTED_SET (t, SRP_SIGNED);
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+ emit_move_insn (operands[0], t);
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+ DONE;
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+ }
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+})
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+
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+(define_expand "<optab><mode>3"
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+ [(set (match_operand:GPR 0 "register_operand" "=r")
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+ (arith_w:GPR (match_operand:GPR 1 "register_operand" "r")
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+ (match_operand:GPR 2 "register_operand" "r")))]
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+ ""
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+{
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+ if (TARGET_64BIT && <MODE>mode == SImode)
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+ {
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+ rtx t = gen_reg_rtx (DImode);
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+ emit_insn (gen_<optab>si3_extend (t, operands[1], operands[2]));
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+ t = gen_lowpart (SImode, t);
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+ SUBREG_PROMOTED_VAR_P (t) = 1;
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+ SUBREG_PROMOTED_SET (t, SRP_SIGNED);
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+ emit_move_insn (operands[0], t);
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+ DONE;
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+ }
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+})
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+
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;;
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;; ....................
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;;
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@@ -781,7 +825,7 @@
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[(set_attr "type" "fadd")
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(set_attr "mode" "<UNITMODE>")])
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-(define_insn "sub<mode>3"
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+(define_insn "*sub<mode>3"
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[(set (match_operand:GPR 0 "register_operand" "=r")
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(minus:GPR (match_operand:GPR 1 "register_operand" "r")
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(match_operand:GPR 2 "register_operand" "r")))]
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@@ -791,7 +835,7 @@
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(set_attr "mode" "<MODE>")])
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-(define_insn "*subsi3_extended"
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+(define_insn "subsi3_extend"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI
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(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
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@@ -818,7 +862,7 @@
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[(set_attr "type" "fmul")
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(set_attr "mode" "<MODE>")])
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-(define_insn "mul<mode>3"
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+(define_insn "*mul<mode>3"
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[(set (match_operand:GPR 0 "register_operand" "=r")
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(mult:GPR (match_operand:GPR 1 "register_operand" "r")
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(match_operand:GPR 2 "register_operand" "r")))]
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@@ -827,7 +871,7 @@
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[(set_attr "type" "imul")
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(set_attr "mode" "<MODE>")])
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-(define_insn "*mulsi3_extended"
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+(define_insn "mulsi3_extend"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI
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(mult:SI (match_operand:SI 1 "register_operand" "r")
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@@ -1001,8 +1045,19 @@
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(match_operand:GPR 2 "register_operand")))]
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""
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{
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- if (GET_MODE (operands[0]) == SImode && TARGET_64BIT && !ISA_HAS_DIV32)
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+ if (GET_MODE (operands[0]) == SImode && TARGET_64BIT)
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{
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+ if (ISA_HAS_DIV32)
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+ {
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+ rtx t = gen_reg_rtx (DImode);
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+ emit_insn (gen_<optab>si3_extended (t, operands[1], operands[2]));
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+ t = gen_lowpart (SImode, t);
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+ SUBREG_PROMOTED_VAR_P (t) = 1;
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+ SUBREG_PROMOTED_SET (t, SRP_SIGNED);
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+ emit_move_insn (operands[0], t);
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+ DONE;
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+ }
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+
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rtx reg1 = gen_reg_rtx (DImode);
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rtx reg2 = gen_reg_rtx (DImode);
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rtx rd = gen_reg_rtx (DImode);
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@@ -1038,7 +1093,7 @@
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(define_insn "<optab>si3_extended"
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[(set (match_operand:DI 0 "register_operand" "=r,&r,&r")
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- (sign_extend
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+ (sign_extend:DI
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(any_div:SI (match_operand:SI 1 "register_operand" "r,r,0")
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(match_operand:SI 2 "register_operand" "r,r,r"))))]
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"TARGET_64BIT && ISA_HAS_DIV32"
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@@ -2981,7 +3036,7 @@
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;;
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;; ....................
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-(define_insn "<optab><mode>3"
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+(define_insn "*<optab><mode>3"
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[(set (match_operand:GPR 0 "register_operand" "=r")
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(any_shift:GPR (match_operand:GPR 1 "register_operand" "r")
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(match_operand:SI 2 "arith_operand" "rI")))]
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@@ -2996,7 +3051,7 @@
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[(set_attr "type" "shift")
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(set_attr "mode" "<MODE>")])
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-(define_insn "*<optab>si3_extend"
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+(define_insn "<optab>si3_extend"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI
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(any_shift:SI (match_operand:SI 1 "register_operand" "r")
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@@ -3011,7 +3066,7 @@
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[(set_attr "type" "shift")
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(set_attr "mode" "SI")])
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-(define_insn "rotr<mode>3"
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+(define_insn "*rotr<mode>3"
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[(set (match_operand:GPR 0 "register_operand" "=r,r")
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(rotatert:GPR (match_operand:GPR 1 "register_operand" "r,r")
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(match_operand:SI 2 "arith_operand" "r,I")))]
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@@ -3040,6 +3095,19 @@
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""
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{
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operands[3] = gen_reg_rtx (SImode);
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+
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+ if (TARGET_64BIT && <MODE>mode == SImode)
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+ {
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+ rtx t = gen_reg_rtx (DImode);
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+
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+ emit_insn (gen_negsi2 (operands[3], operands[2]));
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+ emit_insn (gen_rotrsi3_extend (t, operands[1], operands[3]));
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+ t = gen_lowpart (SImode, t);
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+ SUBREG_PROMOTED_VAR_P (t) = 1;
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+ SUBREG_PROMOTED_SET (t, SRP_SIGNED);
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+ emit_move_insn (operands[0], t);
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+ DONE;
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+ }
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});
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;; The following templates were added to generate "bstrpick.d + alsl.d"
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@@ -4061,26 +4129,45 @@
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(define_insn "bytepick_w_<bytepick_imm>"
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[(set (match_operand:SI 0 "register_operand" "=r")
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- (ior:SI (lshiftrt (match_operand:SI 1 "register_operand" "r")
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- (const_int <bytepick_w_lshiftrt_amount>))
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- (ashift (match_operand:SI 2 "register_operand" "r")
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- (const_int bytepick_w_ashift_amount))))]
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+ (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
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+ (const_int <bytepick_w_lshiftrt_amount>))
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+ (ashift:SI (match_operand:SI 2 "register_operand" "r")
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+ (const_int bytepick_w_ashift_amount))))]
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""
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"bytepick.w\t%0,%1,%2,<bytepick_imm>"
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[(set_attr "mode" "SI")])
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+(define_mode_attr bitsize [(QI "8") (HI "16")])
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+(define_mode_attr bytepick_imm [(QI "3") (HI "2")])
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+(define_mode_attr bytepick_w_ashift_amount [(QI "24") (HI "16")])
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+
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(define_insn "bytepick_w_<bytepick_imm>_extend"
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[(set (match_operand:DI 0 "register_operand" "=r")
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- (sign_extend:DI
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- (subreg:SI
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- (ior:DI (subreg:DI (lshiftrt
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- (match_operand:SI 1 "register_operand" "r")
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- (const_int <bytepick_w_lshiftrt_amount>)) 0)
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- (subreg:DI (ashift
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- (match_operand:SI 2 "register_operand" "r")
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- (const_int bytepick_w_ashift_amount)) 0)) 0)))]
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+ (ior:DI
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+ (ashift:DI
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+ (sign_extend:DI
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+ (subreg:SHORT (match_operand:DI 1 "register_operand" "r") 0))
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+ (const_int <bytepick_w_ashift_amount>))
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+ (zero_extract:DI (match_operand:DI 2 "register_operand" "r")
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+ (const_int <bytepick_w_ashift_amount>)
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+ (const_int <bitsize>))))]
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"TARGET_64BIT"
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- "bytepick.w\t%0,%1,%2,<bytepick_imm>"
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+ "bytepick.w\t%0,%2,%1,<bytepick_imm>"
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+ [(set_attr "mode" "SI")])
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+
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+(define_insn "bytepick_w_1_extend"
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+ [(set (match_operand:DI 0 "register_operand" "=r")
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+ (ior:DI
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+ (ashift:DI
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+ (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
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+ (const_int 24)
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+ (const_int 0))
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+ (const_int 8))
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+ (zero_extract:DI (match_operand:DI 2 "register_operand" "r")
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+ (const_int 8)
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+ (const_int 24))))]
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+ "TARGET_64BIT"
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+ "bytepick.w\t%0,%2,%1,1"
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[(set_attr "mode" "SI")])
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(define_insn "bytepick_d_<bytepick_imm>"
|
||
|
|
diff --git a/gcc/testsuite/gcc.target/loongarch/bitwise_extend.c b/gcc/testsuite/gcc.target/loongarch/bitwise_extend.c
|
||
|
|
new file mode 100644
|
||
|
|
index 000000000..c2bc489a7
|
||
|
|
--- /dev/null
|
||
|
|
+++ b/gcc/testsuite/gcc.target/loongarch/bitwise_extend.c
|
||
|
|
@@ -0,0 +1,45 @@
|
||
|
|
+/* { dg-do compile } */
|
||
|
|
+/* { dg-options "-O2 -march=loongarch64 -mdiv32" } */
|
||
|
|
+/* { dg-final { scan-assembler-not "slli\\.w" } } */
|
||
|
|
+
|
||
|
|
+int
|
||
|
|
+f1 (int a, int b)
|
||
|
|
+{
|
||
|
|
+ return (a << b) | b;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+int
|
||
|
|
+f2 (int a, int b)
|
||
|
|
+{
|
||
|
|
+ return (a - b) | b;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+int
|
||
|
|
+f3 (int a, int b)
|
||
|
|
+{
|
||
|
|
+ return (a * b) | b;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+int
|
||
|
|
+f4 (int a, int b)
|
||
|
|
+{
|
||
|
|
+ return (unsigned) a >> b | (unsigned) a << (32 - b) | b;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+int
|
||
|
|
+f5 (int a, int b)
|
||
|
|
+{
|
||
|
|
+ return (unsigned) a << b | (unsigned) a >> (32 - b) | b;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+int
|
||
|
|
+f6 (int a, int b)
|
||
|
|
+{
|
||
|
|
+ return (a % b) | b;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+int
|
||
|
|
+f7 (int a, int b)
|
||
|
|
+{
|
||
|
|
+ return (a + b) | b;
|
||
|
|
+}
|
||
|
|
--
|
||
|
|
2.43.0
|
||
|
|
|