!19 LoongArch: sync from upstream

From: @ticat-fp 
Reviewed-by: @eastb233 
Signed-off-by: @eastb233

0001-LoongArch-Remove-the-definition-of-the-macro-LOGICAL.patch

@@ -0,0 +1,33 @@
+From 80709e422ee33977d9e50eb18a03a537afee5d6f Mon Sep 17 00:00:00 2001
+From: Lulu Cheng <chenglulu@loongson.cn>
+Date: Thu, 20 Feb 2025 11:00:49 +0800
+Subject: [PATCH 01/20] LoongArch: Remove the definition of the macro
+ LOGICAL_OP_NON_SHORT_CIRCUIT under the architecture and use the
+ defaultdefinition instead.
+
+In some cases, setting this macro as the default can reduce the number of conditional
+branch instructions.
+
+gcc/ChangeLog:
+
+  * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Remove the macro
+  definition.
+---
+ gcc/config/loongarch/loongarch.h | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h
+index 6be1029be..4efe23059 100644
+--- a/gcc/config/loongarch/loongarch.h
++++ b/gcc/config/loongarch/loongarch.h
+@@ -868,7 +868,6 @@ typedef struct {
+    1 is the default; other values are interpreted relative to that.  */
+ 
+ #define BRANCH_COST(speed_p, predictable_p) la_branch_cost
+-#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
+ 
+ /* Return the asm template for a conditional branch instruction.
+    OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
+-- 
+2.43.0
+

0002-LoongArch-Fix-mode-size-comparision-in-loongarch_exp.patch

@@ -0,0 +1,36 @@
+From 52947dd357d48cf80d4bef4ef506d9b772eeb8db Mon Sep 17 00:00:00 2001
+From: Xi Ruoyao <xry111@xry111.site>
+Date: Wed, 12 Jun 2024 11:01:53 +0800
+Subject: [PATCH 02/20] LoongArch: Fix mode size comparision in
+ loongarch_expand_conditional_move
+
+We were comparing a mode size with word_mode, but word_mode is an enum
+value thus this does not really make any sense.  (Un)luckily E_DImode
+happens to be 8 so this seemed to work, but let's make it correct so it
+won't blow up when we add LA32 support or add another machine mode...
+
+gcc/ChangeLog:
+
+	* config/loongarch/loongarch.cc
+	(loongarch_expand_conditional_move): Compare mode size with
+	UNITS_PER_WORD instead of word_mode.
+---
+ gcc/config/loongarch/loongarch.cc | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
+index 4b456e3ef..de01b448f 100644
+--- a/gcc/config/loongarch/loongarch.cc
++++ b/gcc/config/loongarch/loongarch.cc
+@@ -5352,7 +5352,7 @@ loongarch_expand_conditional_move (rtx *operands)
+     loongarch_emit_float_compare (&code, &op0, &op1);
+   else
+     {
+-      if (GET_MODE_SIZE (GET_MODE (op0)) < word_mode)
++      if (GET_MODE_SIZE (GET_MODE (op0)) < UNITS_PER_WORD)
+ 	{
+ 	  promote_op[0] = (REG_P (op0) && REG_P (operands[2]) &&
+ 			   REGNO (op0) == REGNO (operands[2]));
+-- 
+2.43.0
+

0003-LoongArch-Use-bstrins-for-value-1u-const.patch

@@ -0,0 +1,135 @@
+From 0ee2750446865210091658306fe822a880d87035 Mon Sep 17 00:00:00 2001
+From: Xi Ruoyao <xry111@xry111.site>
+Date: Sun, 9 Jun 2024 14:43:48 +0800
+Subject: [PATCH 03/20] LoongArch: Use bstrins for "value & (-1u << const)"
+
+A move/bstrins pair is as fast as a (addi.w|lu12i.w|lu32i.d|lu52i.d)/and
+pair, and twice fast as a srli/slli pair.  When the src reg and the dst
+reg happens to be the same, the move instruction can be optimized away.
+
+gcc/ChangeLog:
+
+	* config/loongarch/predicates.md (high_bitmask_operand): New
+	predicate.
+	* config/loongarch/constraints.md (Yy): New constriant.
+	* config/loongarch/loongarch.md (and<mode>3_align): New
+	define_insn_and_split.
+
+gcc/testsuite/ChangeLog:
+
+	* gcc.target/loongarch/bstrins-1.c: New test.
+	* gcc.target/loongarch/bstrins-2.c: New test.
+---
+ gcc/config/loongarch/constraints.md            |  5 +++++
+ gcc/config/loongarch/loongarch.md              | 17 +++++++++++++++++
+ gcc/config/loongarch/predicates.md             |  4 ++++
+ gcc/testsuite/gcc.target/loongarch/bstrins-1.c |  9 +++++++++
+ gcc/testsuite/gcc.target/loongarch/bstrins-2.c | 14 ++++++++++++++
+ 5 files changed, 49 insertions(+)
+ create mode 100644 gcc/testsuite/gcc.target/loongarch/bstrins-1.c
+ create mode 100644 gcc/testsuite/gcc.target/loongarch/bstrins-2.c
+
+diff --git a/gcc/config/loongarch/constraints.md b/gcc/config/loongarch/constraints.md
+index f07d31650..12cf5e292 100644
+--- a/gcc/config/loongarch/constraints.md
++++ b/gcc/config/loongarch/constraints.md
+@@ -94,6 +94,7 @@
+ ;;       "A constant @code{move_operand} that can be safely loaded using
+ ;;	  @code{la}."
+ ;;    "Yx"
++;;    "Yy"
+ ;; "Z" -
+ ;;    "ZC"
+ ;;      "A memory operand whose address is formed by a base register and offset
+@@ -291,6 +292,10 @@
+    "@internal"
+    (match_operand 0 "low_bitmask_operand"))
+ 
++(define_constraint "Yy"
++   "@internal"
++   (match_operand 0 "high_bitmask_operand"))
++
+ (define_constraint "YI"
+   "@internal
+    A replicated vector const in which the replicated value is in the range
+diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
+index 5c80c169c..25c1d323b 100644
+--- a/gcc/config/loongarch/loongarch.md
++++ b/gcc/config/loongarch/loongarch.md
+@@ -1542,6 +1542,23 @@
+   [(set_attr "move_type" "pick_ins")
+    (set_attr "mode" "<MODE>")])
+ 
++(define_insn_and_split "and<mode>3_align"
++  [(set (match_operand:GPR 0 "register_operand" "=r")
++	(and:GPR (match_operand:GPR 1 "register_operand" "r")
++		 (match_operand:GPR 2 "high_bitmask_operand" "Yy")))]
++  ""
++  "#"
++  ""
++  [(set (match_dup 0) (match_dup 1))
++   (set (zero_extract:GPR (match_dup 0) (match_dup 2) (const_int 0))
++	(const_int 0))]
++{
++  int len;
++
++  len = low_bitmask_len (<MODE>mode, ~INTVAL (operands[2]));
++  operands[2] = GEN_INT (len);
++})
++
+ (define_insn_and_split "*bstrins_<mode>_for_mask"
+   [(set (match_operand:GPR 0 "register_operand" "=r")
+ 	(and:GPR (match_operand:GPR 1 "register_operand" "r")
+diff --git a/gcc/config/loongarch/predicates.md b/gcc/config/loongarch/predicates.md
+index eba7f246c..58e406ea5 100644
+--- a/gcc/config/loongarch/predicates.md
++++ b/gcc/config/loongarch/predicates.md
+@@ -293,6 +293,10 @@
+   (and (match_code "const_int")
+        (match_test "low_bitmask_len (mode, INTVAL (op)) > 12")))
+ 
++(define_predicate "high_bitmask_operand"
++  (and (match_code "const_int")
++       (match_test "low_bitmask_len (mode, ~INTVAL (op)) > 0")))
++
+ (define_predicate "d_operand"
+   (and (match_code "reg")
+        (match_test "GP_REG_P (REGNO (op))")))
+diff --git a/gcc/testsuite/gcc.target/loongarch/bstrins-1.c b/gcc/testsuite/gcc.target/loongarch/bstrins-1.c
+new file mode 100644
+index 000000000..7cb3a9523
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/loongarch/bstrins-1.c
+@@ -0,0 +1,9 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */
++/* { dg-final { scan-assembler "bstrins\\.d\t\\\$r4,\\\$r0,4,0" } } */
++
++long
++x (long a)
++{
++  return a & -32;
++}
+diff --git a/gcc/testsuite/gcc.target/loongarch/bstrins-2.c b/gcc/testsuite/gcc.target/loongarch/bstrins-2.c
+new file mode 100644
+index 000000000..9777f502e
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/loongarch/bstrins-2.c
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */
++/* { dg-final { scan-assembler "bstrins\\.d\t\\\$r\[0-9\]+,\\\$r0,4,0" } } */
++
++struct aligned_buffer {
++  _Alignas(32) char x[1024];
++};
++
++extern int f(char *);
++int g(void)
++{
++  struct aligned_buffer buf;
++  return f(buf.x);
++}
+-- 
+2.43.0
+

0004-LoongArch-Tweak-IOR-rtx_cost-for-bstrins.patch

@@ -0,0 +1,158 @@
+From c730b5accf8810568763704e0ed321d6774c2ea0 Mon Sep 17 00:00:00 2001
+From: Xi Ruoyao <xry111@xry111.site>
+Date: Sat, 15 Jun 2024 18:29:43 +0800
+Subject: [PATCH 04/20] LoongArch: Tweak IOR rtx_cost for bstrins
+
+Consider
+
+    c &= 0xfff;
+    a &= ~0xfff;
+    b &= ~0xfff;
+    a |= c;
+    b |= c;
+
+This can be done with 2 bstrins instructions.  But we need to recognize
+it in loongarch_rtx_costs or the compiler will not propagate "c & 0xfff"
+forward.
+
+gcc/ChangeLog:
+
+	* config/loongarch/loongarch.cc:
+	(loongarch_use_bstrins_for_ior_with_mask): Split the main logic
+	into ...
+	(loongarch_use_bstrins_for_ior_with_mask_1): ... here.
+	(loongarch_rtx_costs): Special case for IOR those can be
+	implemented with bstrins.
+
+gcc/testsuite/ChangeLog;
+
+	* gcc.target/loongarch/bstrins-3.c: New test.
+---
+ gcc/config/loongarch/loongarch.cc             | 73 ++++++++++++++-----
+ .../gcc.target/loongarch/bstrins-3.c          | 16 ++++
+ 2 files changed, 72 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/loongarch/bstrins-3.c
+
+diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
+index de01b448f..7476e46ff 100644
+--- a/gcc/config/loongarch/loongarch.cc
++++ b/gcc/config/loongarch/loongarch.cc
+@@ -3681,6 +3681,27 @@ loongarch_set_reg_reg_piece_cost (machine_mode mode, unsigned int units)
+   return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
+ }
+ 
++static int
++loongarch_use_bstrins_for_ior_with_mask_1 (machine_mode mode,
++					   unsigned HOST_WIDE_INT mask1,
++					   unsigned HOST_WIDE_INT mask2)
++{
++  if (mask1 != ~mask2 || !mask1 || !mask2)
++    return 0;
++
++  /* Try to avoid a right-shift.  */
++  if (low_bitmask_len (mode, mask1) != -1)
++    return -1;
++
++  if (low_bitmask_len (mode, mask2 >> (ffs_hwi (mask2) - 1)) != -1)
++    return 1;
++
++  if (low_bitmask_len (mode, mask1 >> (ffs_hwi (mask1) - 1)) != -1)
++    return -1;
++
++  return 0;
++}
++
+ /* Return the cost of moving between two registers of mode MODE.  */
+ 
+ static int
+@@ -3812,6 +3833,38 @@ loongarch_rtx_costs (rtx x, machine_mode mode, int outer_code,
+       /* Fall through.  */
+ 
+     case IOR:
++      {
++	rtx op[2] = {XEXP (x, 0), XEXP (x, 1)};
++	if (GET_CODE (op[0]) == AND && GET_CODE (op[1]) == AND
++	    && (mode == SImode || (TARGET_64BIT && mode == DImode)))
++	  {
++	    rtx rtx_mask0 = XEXP (op[0], 1), rtx_mask1 = XEXP (op[1], 1);
++	    if (CONST_INT_P (rtx_mask0) && CONST_INT_P (rtx_mask1))
++	      {
++		unsigned HOST_WIDE_INT mask0 = UINTVAL (rtx_mask0);
++		unsigned HOST_WIDE_INT mask1 = UINTVAL (rtx_mask1);
++		if (loongarch_use_bstrins_for_ior_with_mask_1 (mode,
++							       mask0,
++							       mask1))
++		  {
++		    /* A bstrins instruction */
++		    *total = COSTS_N_INSNS (1);
++
++		    /* A srai instruction */
++		    if (low_bitmask_len (mode, mask0) == -1
++			&& low_bitmask_len (mode, mask1) == -1)
++		      *total += COSTS_N_INSNS (1);
++
++		    for (int i = 0; i < 2; i++)
++		      *total += set_src_cost (XEXP (op[i], 0), mode, speed);
++
++		    return true;
++		  }
++	      }
++	  }
++      }
++
++      /* Fall through.  */
+     case XOR:
+       /* Double-word operations use two single-word operations.  */
+       *total = loongarch_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
+@@ -5796,23 +5849,9 @@ bool loongarch_pre_reload_split (void)
+ int
+ loongarch_use_bstrins_for_ior_with_mask (machine_mode mode, rtx *op)
+ {
+-  unsigned HOST_WIDE_INT mask1 = UINTVAL (op[2]);
+-  unsigned HOST_WIDE_INT mask2 = UINTVAL (op[4]);
+-
+-  if (mask1 != ~mask2 || !mask1 || !mask2)
+-    return 0;
+-
+-  /* Try to avoid a right-shift.  */
+-  if (low_bitmask_len (mode, mask1) != -1)
+-    return -1;
+-
+-  if (low_bitmask_len (mode, mask2 >> (ffs_hwi (mask2) - 1)) != -1)
+-    return 1;
+-
+-  if (low_bitmask_len (mode, mask1 >> (ffs_hwi (mask1) - 1)) != -1)
+-    return -1;
+-
+-  return 0;
++  return loongarch_use_bstrins_for_ior_with_mask_1 (mode,
++						    UINTVAL (op[2]),
++						    UINTVAL (op[4]));
+ }
+ 
+ /* Rewrite a MEM for simple load/store under -mexplicit-relocs=auto
+diff --git a/gcc/testsuite/gcc.target/loongarch/bstrins-3.c b/gcc/testsuite/gcc.target/loongarch/bstrins-3.c
+new file mode 100644
+index 000000000..13762bdef
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/loongarch/bstrins-3.c
+@@ -0,0 +1,16 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-rtl-final" } */
++/* { dg-final { scan-rtl-dump-times "insv\[sd\]i" 2 "final" } } */
++
++struct X {
++  long a, b;
++};
++
++struct X
++test (long a, long b, long c)
++{
++  c &= 0xfff;
++  a &= ~0xfff;
++  b &= ~0xfff;
++  return (struct X){.a = a | c, .b = b | c}; 
++}
+-- 
+2.43.0
+

0005-LoongArch-NFC-Dedup-and-sort-the-comment-in-loongarc.patch

@@ -0,0 +1,44 @@
+From 8f8948954cabfc92cc4c60f83bc54f7f7835738e Mon Sep 17 00:00:00 2001
+From: Xi Ruoyao <xry111@xry111.site>
+Date: Sun, 16 Jun 2024 12:22:40 +0800
+Subject: [PATCH 05/20] LoongArch: NFC: Dedup and sort the comment in
+ loongarch_print_operand_reloc
+
+gcc/ChangeLog:
+
+	* config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
+	Dedup and sort the comment describing modifiers.
+---
+ gcc/config/loongarch/loongarch.cc | 10 +---------
+ 1 file changed, 1 insertion(+), 9 deletions(-)
+
+diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
+index 7476e46ff..9148ebcbc 100644
+--- a/gcc/config/loongarch/loongarch.cc
++++ b/gcc/config/loongarch/loongarch.cc
+@@ -6132,21 +6132,13 @@ loongarch_print_operand_reloc (FILE *file, rtx op, bool hi64_part,
+    'T'	Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
+ 	      'z' for (eq:?I ...), 'n' for (ne:?I ...).
+    't'	Like 'T', but with the EQ/NE cases reversed
+-   'F'	Print the FPU branch condition for comparison OP.
+-   'W'	Print the inverse of the FPU branch condition for comparison OP.
+-   'w'	Print a LSX register.
+    'u'	Print a LASX register.
+-   'T'	Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
+-	      'z' for (eq:?I ...), 'n' for (ne:?I ...).
+-   't'	Like 'T', but with the EQ/NE cases reversed
+-   'Y'	Print loongarch_fp_conditions[INTVAL (OP)]
+-   'Z'	Print OP and a comma for 8CC, otherwise print nothing.
+-   'z'	Print $0 if OP is zero, otherwise print OP normally.
+    'v'	Print the insn size suffix b, h, w or d for vector modes V16QI, V8HI,
+ 	  V4SI, V2SI, and w, d for vector modes V4SF, V2DF respectively.
+    'V'	Print exact log2 of CONST_INT OP element 0 of a replicated
+ 	  CONST_VECTOR in decimal.
+    'W'	Print the inverse of the FPU branch condition for comparison OP.
++   'w'	Print a LSX register.
+    'X'	Print CONST_INT OP in hexadecimal format.
+    'x'	Print the low 16 bits of CONST_INT OP in hexadecimal format.
+    'Y'	Print loongarch_fp_conditions[INTVAL (OP)]
+-- 
+2.43.0
+

0006-LoongArch-Fix-explicit-relocs-extreme-tls-desc.c-tes.patch

@@ -0,0 +1,45 @@
+From ed4da773e214d0b2fa0dfb5136ba8f839c6a7a59 Mon Sep 17 00:00:00 2001
+From: Lulu Cheng <chenglulu@loongson.cn>
+Date: Fri, 28 Jun 2024 15:04:26 +0800
+Subject: [PATCH 06/20] LoongArch: Fix explicit-relocs-{extreme-,}tls-desc.c
+ tests.
+
+After r15-1579, ADD and LD/ST pairs will be merged into LDX/STX.
+Cause these two tests to fail. To guarantee that these two tests pass,
+add the compilation option '-fno-late-combine-instructions'.
+
+gcc/testsuite/ChangeLog:
+
+	* gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c:
+	Add compilation options '-fno-late-combine-instructions'.
+	* gcc.target/loongarch/explicit-relocs-tls-desc.c: Likewise.
+---
+ .../gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c     | 2 +-
+ gcc/testsuite/gcc.target/loongarch/explicit-relocs-tls-desc.c   | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c
+index 3797556e1..e9eb0d6f7 100644
+--- a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c
++++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fPIC -mexplicit-relocs -mtls-dialect=desc -mcmodel=extreme" } */
++/* { dg-options "-O2 -fPIC -mexplicit-relocs -mtls-dialect=desc -mcmodel=extreme -fno-late-combine-instructions" } */
+ 
+ __thread int a __attribute__((visibility("hidden")));
+ extern __thread int b __attribute__((visibility("default")));
+diff --git a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-tls-desc.c b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-tls-desc.c
+index f66903091..fed478458 100644
+--- a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-tls-desc.c
++++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-tls-desc.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fPIC -mexplicit-relocs -mtls-dialect=desc" } */
++/* { dg-options "-O2 -fPIC -mexplicit-relocs -mtls-dialect=desc -fno-late-combine-instructions" } */
+ 
+ __thread int a __attribute__((visibility("hidden")));
+ extern __thread int b __attribute__((visibility("default")));
+-- 
+2.43.0
+

0007-LoongArch-Define-loongarch_insn_cost-and-set-the-cos.patch

@@ -0,0 +1,70 @@
+From 2c763d7ec71ef51f8704c8c3444dd5ab9144dbc6 Mon Sep 17 00:00:00 2001
+From: Lulu Cheng <chenglulu@loongson.cn>
+Date: Fri, 28 Jun 2024 15:09:48 +0800
+Subject: [PATCH 07/20] LoongArch: Define loongarch_insn_cost and set the cost
+ of movcf2gr and movgr2cf.
+
+The following two FAIL items have been fixed:
+
+FAIL: gcc.target/loongarch/movcf2gr-via-fr.c scan-assembler movcf2fr\\t\\\\\$f[0-9]+,\\\\\$fcc
+FAIL: gcc.target/loongarch/movcf2gr-via-fr.c scan-assembler movfr2gr\\\\.s\\t\\\\\$r4
+
+gcc/ChangeLog:
+
+	* config/loongarch/loongarch.cc (loongarch_insn_cost):
+	New function.
+	(TARGET_INSN_COST): New macro.
+---
+ gcc/config/loongarch/loongarch.cc | 29 +++++++++++++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
+index 9148ebcbc..2b2f3c613 100644
+--- a/gcc/config/loongarch/loongarch.cc
++++ b/gcc/config/loongarch/loongarch.cc
+@@ -4372,6 +4372,33 @@ loongarch_address_cost (rtx addr, machine_mode mode,
+   return loongarch_address_insns (addr, mode, false);
+ }
+ 
++/* Implement TARGET_INSN_COST.  */
++
++static int
++loongarch_insn_cost (rtx_insn *insn, bool speed)
++{
++  rtx x = PATTERN (insn);
++  int cost = pattern_cost (x, speed);
++
++  /* On LA464, prevent movcf2fr and movfr2gr from merging into movcf2gr.  */
++  if (GET_CODE (x) == SET
++      && GET_MODE (XEXP (x, 0)) == FCCmode)
++    {
++      rtx dest, src;
++      dest = XEXP (x, 0);
++      src = XEXP (x, 1);
++
++      if (REG_P (dest) && REG_P (src))
++	{
++	  if (GP_REG_P (REGNO (dest)) && FCC_REG_P (REGNO (src)))
++	    cost = loongarch_cost->movcf2gr;
++	  else if (FCC_REG_P (REGNO (dest)) && GP_REG_P (REGNO (src)))
++	    cost = loongarch_cost->movgr2cf;
++	}
++    }
++  return cost;
++}
++
+ /* Return one word of double-word value OP, taking into account the fixed
+    endianness of certain registers.  HIGH_P is true to select the high part,
+    false to select the low part.  */
+@@ -11093,6 +11120,8 @@ loongarch_asm_code_end (void)
+ #define TARGET_RTX_COSTS loongarch_rtx_costs
+ #undef TARGET_ADDRESS_COST
+ #define TARGET_ADDRESS_COST loongarch_address_cost
++#undef TARGET_INSN_COST
++#define TARGET_INSN_COST loongarch_insn_cost
+ #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
+ #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
+   loongarch_builtin_vectorization_cost
+-- 
+2.43.0
+

0008-LoongArch-Remove-unreachable-codes.patch

@@ -0,0 +1,249 @@
+From b20fb490bf25a076b373fea56cca6c8191584150 Mon Sep 17 00:00:00 2001
+From: Lulu Cheng <chenglulu@loongson.cn>
+Date: Thu, 4 Jul 2024 15:00:40 +0800
+Subject: [PATCH 08/20] LoongArch: Remove unreachable codes.
+
+gcc/ChangeLog:
+
+	* config/loongarch/loongarch.cc
+	(loongarch_split_move): Delete.
+	(loongarch_hard_regno_mode_ok_uncached): Likewise.
+	* config/loongarch/loongarch.md
+	(move_doubleword_fpr<mode>): Likewise.
+	(load_low<mode>): Likewise.
+	(load_high<mode>): Likewise.
+	(store_word<mode>): Likewise.
+	(movgr2frh<mode>): Likewise.
+	(movfrh2gr<mode>): Likewise.
+---
+ gcc/config/loongarch/loongarch.cc |  47 +++----------
+ gcc/config/loongarch/loongarch.md | 109 ------------------------------
+ 2 files changed, 8 insertions(+), 148 deletions(-)
+
+diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
+index 2b2f3c613..aabada83d 100644
+--- a/gcc/config/loongarch/loongarch.cc
++++ b/gcc/config/loongarch/loongarch.cc
+@@ -4462,42 +4462,13 @@ loongarch_split_move_p (rtx dest, rtx src)
+ void
+ loongarch_split_move (rtx dest, rtx src)
+ {
+-  rtx low_dest;
+-
+   gcc_checking_assert (loongarch_split_move_p (dest, src));
+   if (LSX_SUPPORTED_MODE_P (GET_MODE (dest)))
+     loongarch_split_128bit_move (dest, src);
+   else if (LASX_SUPPORTED_MODE_P (GET_MODE (dest)))
+     loongarch_split_256bit_move (dest, src);
+-  else if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
+-    {
+-      if (!TARGET_64BIT && GET_MODE (dest) == DImode)
+-	emit_insn (gen_move_doubleword_fprdi (dest, src));
+-      else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
+-	emit_insn (gen_move_doubleword_fprdf (dest, src));
+-      else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
+-	emit_insn (gen_move_doubleword_fprtf (dest, src));
+-      else
+-	gcc_unreachable ();
+-    }
+   else
+-    {
+-      /* The operation can be split into two normal moves.  Decide in
+-	 which order to do them.  */
+-      low_dest = loongarch_subword (dest, false);
+-      if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src))
+-	{
+-	  loongarch_emit_move (loongarch_subword (dest, true),
+-			       loongarch_subword (src, true));
+-	  loongarch_emit_move (low_dest, loongarch_subword (src, false));
+-	}
+-      else
+-	{
+-	  loongarch_emit_move (low_dest, loongarch_subword (src, false));
+-	  loongarch_emit_move (loongarch_subword (dest, true),
+-			       loongarch_subword (src, true));
+-	}
+-    }
++    gcc_unreachable ();
+ }
+ 
+ /* Check if adding an integer constant value for a specific mode can be
+@@ -6746,20 +6717,18 @@ loongarch_hard_regno_mode_ok_uncached (unsigned int regno, machine_mode mode)
+   size = GET_MODE_SIZE (mode);
+   mclass = GET_MODE_CLASS (mode);
+ 
+-  if (GP_REG_P (regno) && !LSX_SUPPORTED_MODE_P (mode)
++  if (GP_REG_P (regno)
++      && !LSX_SUPPORTED_MODE_P (mode)
+       && !LASX_SUPPORTED_MODE_P (mode))
+     return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
+ 
+-  /* For LSX, allow TImode and 128-bit vector modes in all FPR.  */
+-  if (FP_REG_P (regno) && LSX_SUPPORTED_MODE_P (mode))
+-    return true;
+-
+-  /* FIXED ME: For LASX, allow TImode and 256-bit vector modes in all FPR.  */
+-  if (FP_REG_P (regno) && LASX_SUPPORTED_MODE_P (mode))
+-    return true;
+-
+   if (FP_REG_P (regno))
+     {
++      /* Allow 128-bit or 256-bit vector modes in all FPR.  */
++      if (LSX_SUPPORTED_MODE_P (mode)
++	  || LASX_SUPPORTED_MODE_P (mode))
++	return true;
++
+       if (mclass == MODE_FLOAT
+ 	  || mclass == MODE_COMPLEX_FLOAT
+ 	  || mclass == MODE_VECTOR_FLOAT)
+diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
+index 25c1d323b..21890a2d9 100644
+--- a/gcc/config/loongarch/loongarch.md
++++ b/gcc/config/loongarch/loongarch.md
+@@ -400,9 +400,6 @@
+ ;; 64-bit modes for which we provide move patterns.
+ (define_mode_iterator MOVE64 [DI DF])
+ 
+-;; 128-bit modes for which we provide move patterns on 64-bit targets.
+-(define_mode_iterator MOVE128 [TI TF])
+-
+ ;; Iterator for sub-32-bit integer modes.
+ (define_mode_iterator SHORT [QI HI])
+ 
+@@ -421,12 +418,6 @@
+ (define_mode_iterator ANYFI [(SI "TARGET_HARD_FLOAT")
+ 			     (DI "TARGET_DOUBLE_FLOAT")])
+ 
+-;; A mode for which moves involving FPRs may need to be split.
+-(define_mode_iterator SPLITF
+-  [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
+-   (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
+-   (TF "TARGET_64BIT && TARGET_DOUBLE_FLOAT")])
+-
+ ;; A mode for anything with 32 bits or more, and able to be loaded with
+ ;; the same addressing mode as ld.w.
+ (define_mode_iterator LD_AT_LEAST_32_BIT [GPR ANYF])
+@@ -2421,41 +2412,6 @@
+   [(set_attr "move_type" "move,load,store")
+    (set_attr "mode" "DF")])
+ 
+-;; Emit a doubleword move in which exactly one of the operands is
+-;; a floating-point register.  We can't just emit two normal moves
+-;; because of the constraints imposed by the FPU register model;
+-;; see loongarch_can_change_mode_class for details.  Instead, we keep
+-;; the FPR whole and use special patterns to refer to each word of
+-;; the other operand.
+-
+-(define_expand "move_doubleword_fpr<mode>"
+-  [(set (match_operand:SPLITF 0)
+-	(match_operand:SPLITF 1))]
+-  ""
+-{
+-  if (FP_REG_RTX_P (operands[0]))
+-    {
+-      rtx low = loongarch_subword (operands[1], 0);
+-      rtx high = loongarch_subword (operands[1], 1);
+-      emit_insn (gen_load_low<mode> (operands[0], low));
+-      if (!TARGET_64BIT)
+-       emit_insn (gen_movgr2frh<mode> (operands[0], high, operands[0]));
+-      else
+-       emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
+-    }
+-  else
+-    {
+-      rtx low = loongarch_subword (operands[0], 0);
+-      rtx high = loongarch_subword (operands[0], 1);
+-      emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
+-      if (!TARGET_64BIT)
+-       emit_insn (gen_movfrh2gr<mode> (high, operands[1]));
+-      else
+-       emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
+-    }
+-  DONE;
+-})
+-
+ ;; Clear one FCC register
+ 
+ (define_expand "movfcc"
+@@ -2742,49 +2698,6 @@
+   [(set_attr "type" "fcvt")
+    (set_attr "mode" "<ANYF:MODE>")])
+ 
+-;; Load the low word of operand 0 with operand 1.
+-(define_insn "load_low<mode>"
+-  [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
+-	(unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "rJ,m")]
+-		       UNSPEC_LOAD_LOW))]
+-  "TARGET_HARD_FLOAT"
+-{
+-  operands[0] = loongarch_subword (operands[0], 0);
+-  return loongarch_output_move (operands[0], operands[1]);
+-}
+-  [(set_attr "move_type" "mgtf,fpload")
+-   (set_attr "mode" "<HALFMODE>")])
+-
+-;; Load the high word of operand 0 from operand 1, preserving the value
+-;; in the low word.
+-(define_insn "load_high<mode>"
+-  [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
+-	(unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "rJ,m")
+-			(match_operand:SPLITF 2 "register_operand" "0,0")]
+-		       UNSPEC_LOAD_HIGH))]
+-  "TARGET_HARD_FLOAT"
+-{
+-  operands[0] = loongarch_subword (operands[0], 1);
+-  return loongarch_output_move (operands[0], operands[1]);
+-}
+-  [(set_attr "move_type" "mgtf,fpload")
+-   (set_attr "mode" "<HALFMODE>")])
+-
+-;; Store one word of operand 1 in operand 0.  Operand 2 is 1 to store the
+-;; high word and 0 to store the low word.
+-(define_insn "store_word<mode>"
+-  [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=r,m")
+-	(unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
+-			    (match_operand 2 "const_int_operand")]
+-			   UNSPEC_STORE_WORD))]
+-  "TARGET_HARD_FLOAT"
+-{
+-  operands[1] = loongarch_subword (operands[1], INTVAL (operands[2]));
+-  return loongarch_output_move (operands[0], operands[1]);
+-}
+-  [(set_attr "move_type" "mftg,fpstore")
+-   (set_attr "mode" "<HALFMODE>")])
+-
+ ;; Thread-Local Storage
+ 
+ (define_insn "@got_load_tls_desc<mode>"
+@@ -2876,28 +2789,6 @@
+ 	(const_int 4)
+ 	(const_int 2)))])
+ 
+-;; Move operand 1 to the high word of operand 0 using movgr2frh.w, preserving the
+-;; value in the low word.
+-(define_insn "movgr2frh<mode>"
+-  [(set (match_operand:SPLITF 0 "register_operand" "=f")
+-	(unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "rJ")
+-			(match_operand:SPLITF 2 "register_operand" "0")]
+-			UNSPEC_MOVGR2FRH))]
+-  "TARGET_DOUBLE_FLOAT"
+-  "movgr2frh.w\t%z1,%0"
+-  [(set_attr "move_type" "mgtf")
+-   (set_attr "mode" "<HALFMODE>")])
+-
+-;; Move high word of operand 1 to operand 0 using movfrh2gr.s.
+-(define_insn "movfrh2gr<mode>"
+-  [(set (match_operand:<HALFMODE> 0 "register_operand" "=r")
+-	(unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
+-			    UNSPEC_MOVFRH2GR))]
+-  "TARGET_DOUBLE_FLOAT"
+-  "movfrh2gr.s\t%0,%1"
+-  [(set_attr "move_type" "mftg")
+-   (set_attr "mode" "<HALFMODE>")])
+-
+ 
+ ;; Expand in-line code to clear the instruction cache between operand[0] and
+ ;; operand[1].
+-- 
+2.43.0
+

0009-LoongArch-Organize-the-code-related-to-split-move-an.patch

@@ -0,0 +1,413 @@
+From 15a1e38d312fa60c4cbd859b56dba7d19176cee1 Mon Sep 17 00:00:00 2001
+From: Lulu Cheng <chenglulu@loongson.cn>
+Date: Fri, 12 Jul 2024 09:57:40 +0800
+Subject: [PATCH 09/20] LoongArch: Organize the code related to split move and
+ merge the same functions.
+
+gcc/ChangeLog:
+
+	* config/loongarch/loongarch-protos.h
+	(loongarch_split_128bit_move): Delete.
+	(loongarch_split_128bit_move_p): Delete.
+	(loongarch_split_256bit_move): Delete.
+	(loongarch_split_256bit_move_p): Delete.
+	(loongarch_split_vector_move): Add a function declaration.
+	* config/loongarch/loongarch.cc
+	(loongarch_vector_costs::finish_cost): Adjust the code
+	formatting.
+	(loongarch_split_vector_move_p): Merge
+	loongarch_split_128bit_move_p and loongarch_split_256bit_move_p.
+	(loongarch_split_move_p): Merge code.
+	(loongarch_split_move): Likewise.
+	(loongarch_split_128bit_move_p): Delete.
+	(loongarch_split_256bit_move_p): Delete.
+	(loongarch_split_128bit_move): Delete.
+	(loongarch_split_vector_move): Merge loongarch_split_128bit_move
+	and loongarch_split_256bit_move.
+	(loongarch_split_256bit_move): Delete.
+	(loongarch_global_init): Remove the extra semicolon at the
+	end of the function.
+	* config/loongarch/loongarch.md (*movdf_softfloat):  Added a new
+	condition TARGET_64BIT.
+---
+ gcc/config/loongarch/loongarch-protos.h |   5 +-
+ gcc/config/loongarch/loongarch.cc       | 221 ++++++------------------
+ gcc/config/loongarch/loongarch.md       |   1 +
+ 3 files changed, 58 insertions(+), 169 deletions(-)
+
+diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h
+index e238d795a..85f6e8943 100644
+--- a/gcc/config/loongarch/loongarch-protos.h
++++ b/gcc/config/loongarch/loongarch-protos.h
+@@ -85,10 +85,7 @@ extern bool loongarch_split_move_p (rtx, rtx);
+ extern void loongarch_split_move (rtx, rtx);
+ extern bool loongarch_addu16i_imm12_operand_p (HOST_WIDE_INT, machine_mode);
+ extern void loongarch_split_plus_constant (rtx *, machine_mode);
+-extern void loongarch_split_128bit_move (rtx, rtx);
+-extern bool loongarch_split_128bit_move_p (rtx, rtx);
+-extern void loongarch_split_256bit_move (rtx, rtx);
+-extern bool loongarch_split_256bit_move_p (rtx, rtx);
++extern void loongarch_split_vector_move (rtx, rtx);
+ extern const char *loongarch_output_move (rtx, rtx);
+ #ifdef RTX_CODE
+ extern void loongarch_expand_scc (rtx *);
+diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
+index aabada83d..4b6b9e14b 100644
+--- a/gcc/config/loongarch/loongarch.cc
++++ b/gcc/config/loongarch/loongarch.cc
+@@ -4354,10 +4354,10 @@ void
+ loongarch_vector_costs::finish_cost (const vector_costs *scalar_costs)
+ {
+   loop_vec_info loop_vinfo = dyn_cast<loop_vec_info> (m_vinfo);
++
+   if (loop_vinfo)
+-    {
+-      m_suggested_unroll_factor = determine_suggested_unroll_factor (loop_vinfo);
+-    }
++    m_suggested_unroll_factor
++      = determine_suggested_unroll_factor (loop_vinfo);
+ 
+   vector_costs::finish_cost (scalar_costs);
+ }
+@@ -4423,6 +4423,7 @@ loongarch_subword (rtx op, bool high_p)
+   return simplify_gen_subreg (word_mode, op, mode, byte);
+ }
+ 
++static bool loongarch_split_vector_move_p (rtx dest, rtx src);
+ /* Return true if a move from SRC to DEST should be split into two.
+    SPLIT_TYPE describes the split condition.  */
+ 
+@@ -4444,13 +4445,11 @@ loongarch_split_move_p (rtx dest, rtx src)
+ 	return false;
+     }
+ 
+-  /* Check if LSX moves need splitting.  */
+-  if (LSX_SUPPORTED_MODE_P (GET_MODE (dest)))
+-    return loongarch_split_128bit_move_p (dest, src);
+ 
+-  /* Check if LASX moves need splitting.  */
+-  if (LASX_SUPPORTED_MODE_P (GET_MODE (dest)))
+-    return loongarch_split_256bit_move_p (dest, src);
++  /* Check if vector moves need splitting.  */
++  if (LSX_SUPPORTED_MODE_P (GET_MODE (dest))
++      || LASX_SUPPORTED_MODE_P (GET_MODE (dest)))
++    return loongarch_split_vector_move_p (dest, src);
+ 
+   /* Otherwise split all multiword moves.  */
+   return size > UNITS_PER_WORD;
+@@ -4463,10 +4462,9 @@ void
+ loongarch_split_move (rtx dest, rtx src)
+ {
+   gcc_checking_assert (loongarch_split_move_p (dest, src));
+-  if (LSX_SUPPORTED_MODE_P (GET_MODE (dest)))
+-    loongarch_split_128bit_move (dest, src);
+-  else if (LASX_SUPPORTED_MODE_P (GET_MODE (dest)))
+-    loongarch_split_256bit_move (dest, src);
++  if (LSX_SUPPORTED_MODE_P (GET_MODE (dest))
++      || LASX_SUPPORTED_MODE_P (GET_MODE (dest)))
++    loongarch_split_vector_move (dest, src);
+   else
+     gcc_unreachable ();
+ }
+@@ -4588,224 +4586,117 @@ loongarch_output_move_index_float (rtx x, machine_mode mode, bool ldr)
+ 
+   return insn[ldr][index-2];
+ }
+-/* Return true if a 128-bit move from SRC to DEST should be split.  */
+-
+-bool
+-loongarch_split_128bit_move_p (rtx dest, rtx src)
+-{
+-  /* LSX-to-LSX moves can be done in a single instruction.  */
+-  if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
+-    return false;
+-
+-  /* Check for LSX loads and stores.  */
+-  if (FP_REG_RTX_P (dest) && MEM_P (src))
+-    return false;
+-  if (FP_REG_RTX_P (src) && MEM_P (dest))
+-    return false;
+-
+-  /* Check for LSX set to an immediate const vector with valid replicated
+-     element.  */
+-  if (FP_REG_RTX_P (dest)
+-      && loongarch_const_vector_same_int_p (src, GET_MODE (src), -512, 511))
+-    return false;
+-
+-  /* Check for LSX load zero immediate.  */
+-  if (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src)))
+-    return false;
+-
+-  return true;
+-}
+-
+-/* Return true if a 256-bit move from SRC to DEST should be split.  */
++/* Return true if a vector move from SRC to DEST should be split.  */
+ 
+-bool
+-loongarch_split_256bit_move_p (rtx dest, rtx src)
++static bool
++loongarch_split_vector_move_p (rtx dest, rtx src)
+ {
+-  /* LSX-to-LSX moves can be done in a single instruction.  */
++  /* Vector moves can be done in a single instruction.  */
+   if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
+     return false;
+ 
+-  /* Check for LSX loads and stores.  */
++  /* Check for vector loads and stores.  */
+   if (FP_REG_RTX_P (dest) && MEM_P (src))
+     return false;
+   if (FP_REG_RTX_P (src) && MEM_P (dest))
+     return false;
+ 
+-  /* Check for LSX set to an immediate const vector with valid replicated
++  /* Check for vector set to an immediate const vector with valid replicated
+      element.  */
+   if (FP_REG_RTX_P (dest)
+       && loongarch_const_vector_same_int_p (src, GET_MODE (src), -512, 511))
+     return false;
+ 
+-  /* Check for LSX load zero immediate.  */
++  /* Check for vector load zero immediate.  */
+   if (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src)))
+     return false;
+ 
+   return true;
+ }
+ 
+-/* Split a 128-bit move from SRC to DEST.  */
++/* Split a vector move from SRC to DEST.  */
+ 
+ void
+-loongarch_split_128bit_move (rtx dest, rtx src)
++loongarch_split_vector_move (rtx dest, rtx src)
+ {
+   int byte, index;
+-  rtx low_dest, low_src, d, s;
++  rtx s, d;
++  machine_mode mode = GET_MODE (dest);
++  bool lsx_p = LSX_SUPPORTED_MODE_P (mode);
+ 
+   if (FP_REG_RTX_P (dest))
+     {
+       gcc_assert (!MEM_P (src));
+ 
+-      rtx new_dest = dest;
+-      if (!TARGET_64BIT)
+-	{
+-	  if (GET_MODE (dest) != V4SImode)
+-	    new_dest = simplify_gen_subreg (V4SImode, dest, GET_MODE (dest), 0);
+-	}
+-      else
+-	{
+-	  if (GET_MODE (dest) != V2DImode)
+-	    new_dest = simplify_gen_subreg (V2DImode, dest, GET_MODE (dest), 0);
+-	}
+-
+-      for (byte = 0, index = 0; byte < GET_MODE_SIZE (TImode);
+-	   byte += UNITS_PER_WORD, index++)
+-	{
+-	  s = loongarch_subword_at_byte (src, byte);
+-	  if (!TARGET_64BIT)
+-	    emit_insn (gen_lsx_vinsgr2vr_w (new_dest, s, new_dest,
+-					    GEN_INT (1 << index)));
+-	  else
+-	    emit_insn (gen_lsx_vinsgr2vr_d (new_dest, s, new_dest,
+-					    GEN_INT (1 << index)));
+-	}
+-    }
+-  else if (FP_REG_RTX_P (src))
+-    {
+-      gcc_assert (!MEM_P (dest));
+-
+-      rtx new_src = src;
+-      if (!TARGET_64BIT)
+-	{
+-	  if (GET_MODE (src) != V4SImode)
+-	    new_src = simplify_gen_subreg (V4SImode, src, GET_MODE (src), 0);
+-	}
+-      else
+-	{
+-	  if (GET_MODE (src) != V2DImode)
+-	    new_src = simplify_gen_subreg (V2DImode, src, GET_MODE (src), 0);
+-	}
++      rtx (*gen_vinsgr2vr_d) (rtx, rtx, rtx, rtx);
+ 
+-      for (byte = 0, index = 0; byte < GET_MODE_SIZE (TImode);
+-	   byte += UNITS_PER_WORD, index++)
+-	{
+-	  d = loongarch_subword_at_byte (dest, byte);
+-	  if (!TARGET_64BIT)
+-	    emit_insn (gen_lsx_vpickve2gr_w (d, new_src, GEN_INT (index)));
+-	  else
+-	    emit_insn (gen_lsx_vpickve2gr_d (d, new_src, GEN_INT (index)));
+-	}
+-    }
+-  else
+-    {
+-      low_dest = loongarch_subword_at_byte (dest, 0);
+-      low_src = loongarch_subword_at_byte (src, 0);
+-      gcc_assert (REG_P (low_dest) && REG_P (low_src));
+-      /* Make sure the source register is not written before reading.  */
+-      if (REGNO (low_dest) <= REGNO (low_src))
++      if (lsx_p)
+ 	{
+-	  for (byte = 0; byte < GET_MODE_SIZE (TImode);
+-	       byte += UNITS_PER_WORD)
+-	    {
+-	      d = loongarch_subword_at_byte (dest, byte);
+-	      s = loongarch_subword_at_byte (src, byte);
+-	      loongarch_emit_move (d, s);
+-	    }
++	  mode = V2DImode;
++	  gen_vinsgr2vr_d = gen_lsx_vinsgr2vr_d;
+ 	}
+       else
+ 	{
+-	  for (byte = GET_MODE_SIZE (TImode) - UNITS_PER_WORD; byte >= 0;
+-	       byte -= UNITS_PER_WORD)
+-	    {
+-	      d = loongarch_subword_at_byte (dest, byte);
+-	      s = loongarch_subword_at_byte (src, byte);
+-	      loongarch_emit_move (d, s);
+-	    }
++	  mode = V4DImode;
++	  gen_vinsgr2vr_d = gen_lasx_xvinsgr2vr_d;
+ 	}
+-    }
+-}
+-
+-/* Split a 256-bit move from SRC to DEST.  */
+-
+-void
+-loongarch_split_256bit_move (rtx dest, rtx src)
+-{
+-  int byte, index;
+-  rtx low_dest, low_src, d, s;
+-
+-  if (FP_REG_RTX_P (dest))
+-    {
+-      gcc_assert (!MEM_P (src));
+ 
+       rtx new_dest = dest;
+-      if (!TARGET_64BIT)
+-	{
+-	  if (GET_MODE (dest) != V8SImode)
+-	    new_dest = simplify_gen_subreg (V8SImode, dest, GET_MODE (dest), 0);
+-	}
+-      else
+-	{
+-	  if (GET_MODE (dest) != V4DImode)
+-	    new_dest = simplify_gen_subreg (V4DImode, dest, GET_MODE (dest), 0);
+-	}
++
++      if (GET_MODE (dest) != mode)
++	new_dest = simplify_gen_subreg (mode, dest, GET_MODE (dest), 0);
+ 
+       for (byte = 0, index = 0; byte < GET_MODE_SIZE (GET_MODE (dest));
+ 	   byte += UNITS_PER_WORD, index++)
+ 	{
+ 	  s = loongarch_subword_at_byte (src, byte);
+-	  if (!TARGET_64BIT)
+-	    emit_insn (gen_lasx_xvinsgr2vr_w (new_dest, s, new_dest,
+-					      GEN_INT (1 << index)));
+-	  else
+-	    emit_insn (gen_lasx_xvinsgr2vr_d (new_dest, s, new_dest,
+-					      GEN_INT (1 << index)));
++	  emit_insn (gen_vinsgr2vr_d (new_dest, s, new_dest,
++					  GEN_INT (1 << index)));
+ 	}
+     }
+   else if (FP_REG_RTX_P (src))
+     {
+       gcc_assert (!MEM_P (dest));
+ 
+-      rtx new_src = src;
+-      if (!TARGET_64BIT)
++      rtx (*gen_vpickve2gr_d) (rtx, rtx, rtx);
++
++      if (lsx_p)
+ 	{
+-	  if (GET_MODE (src) != V8SImode)
+-	    new_src = simplify_gen_subreg (V8SImode, src, GET_MODE (src), 0);
++	  mode = V2DImode;
++	  gen_vpickve2gr_d = gen_lsx_vpickve2gr_d;
+ 	}
+       else
+ 	{
+-	  if (GET_MODE (src) != V4DImode)
+-	    new_src = simplify_gen_subreg (V4DImode, src, GET_MODE (src), 0);
++	  mode = V4DImode;
++	  gen_vpickve2gr_d = gen_lasx_xvpickve2gr_d;
+ 	}
+ 
++      rtx new_src = src;
++      if (GET_MODE (src) != mode)
++	new_src = simplify_gen_subreg (mode, src, GET_MODE (src), 0);
++
+       for (byte = 0, index = 0; byte < GET_MODE_SIZE (GET_MODE (src));
+ 	   byte += UNITS_PER_WORD, index++)
+ 	{
+ 	  d = loongarch_subword_at_byte (dest, byte);
+-	  if (!TARGET_64BIT)
+-	    emit_insn (gen_lsx_vpickve2gr_w (d, new_src, GEN_INT (index)));
+-	  else
+-	    emit_insn (gen_lsx_vpickve2gr_d (d, new_src, GEN_INT (index)));
++	  emit_insn (gen_vpickve2gr_d (d, new_src, GEN_INT (index)));
+ 	}
+     }
+   else
+     {
++      /* This part of the code is designed to handle the following situations:
++	 (set (reg:V2DI 4 $r4)
++	      (reg:V2DI 6 $r6))
++	 The trigger test case is lsx-mov-1.c.  */
++      rtx low_dest, low_src;
++
+       low_dest = loongarch_subword_at_byte (dest, 0);
+       low_src = loongarch_subword_at_byte (src, 0);
+       gcc_assert (REG_P (low_dest) && REG_P (low_src));
+       /* Make sure the source register is not written before reading.  */
+       if (REGNO (low_dest) <= REGNO (low_src))
+ 	{
+-	  for (byte = 0; byte < GET_MODE_SIZE (TImode);
++	  for (byte = 0; byte < GET_MODE_SIZE (GET_MODE (dest));
+ 	       byte += UNITS_PER_WORD)
+ 	    {
+ 	      d = loongarch_subword_at_byte (dest, byte);
+@@ -4815,8 +4706,8 @@ loongarch_split_256bit_move (rtx dest, rtx src)
+ 	}
+       else
+ 	{
+-	  for (byte = GET_MODE_SIZE (TImode) - UNITS_PER_WORD; byte >= 0;
+-	       byte -= UNITS_PER_WORD)
++	  for (byte = GET_MODE_SIZE (GET_MODE (dest)) - UNITS_PER_WORD;
++	       byte >= 0; byte -= UNITS_PER_WORD)
+ 	    {
+ 	      d = loongarch_subword_at_byte (dest, byte);
+ 	      s = loongarch_subword_at_byte (src, byte);
+@@ -7606,7 +7497,7 @@ loongarch_global_init (void)
+ 
+   /* Function to allocate machine-dependent function status.  */
+   init_machine_status = &loongarch_init_machine_status;
+-};
++}
+ 
+ static void
+ loongarch_reg_init (void)
+diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
+index 21890a2d9..459ad30b9 100644
+--- a/gcc/config/loongarch/loongarch.md
++++ b/gcc/config/loongarch/loongarch.md
+@@ -2406,6 +2406,7 @@
+   [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
+ 	(match_operand:DF 1 "move_operand" "rG,m,rG"))]
+   "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT)
++   && TARGET_64BIT
+    && (register_operand (operands[0], DFmode)
+        || reg_or_0_operand (operands[1], DFmode))"
+   { return loongarch_output_move (operands[0], operands[1]); }
+-- 
+2.43.0
+

0010-LoongArch-Expand-some-SImode-operations-through-si3_.patch

@@ -0,0 +1,364 @@
+From 637e6e0c2f3a38ba9f56174e2e92a3ff39e88344 Mon Sep 17 00:00:00 2001
+From: Xi Ruoyao <xry111@xry111.site>
+Date: Sat, 20 Jul 2024 20:38:13 +0800
+Subject: [PATCH 10/20] LoongArch: Expand some SImode operations through
+ "si3_extend" instructions if TARGET_64BIT
+
+We already had "si3_extend" insns and we hoped the fwprop or combine
+passes can use them to remove unnecessary sign extensions.  But this
+does not always work: for cases like x << 1 | y, the compiler
+tends to do
+
+    (sign_extend:DI
+      (ior:SI (ashift:SI (reg:SI $r4)
+                         (const_int 1))
+              (reg:SI $r5)))
+
+instead of
+
+    (ior:DI (sign_extend:DI (ashift:SI (reg:SI $r4) (const_int 1)))
+            (sign_extend:DI (reg:SI $r5)))
+
+So we cannot match the ashlsi3_extend instruction here and we get:
+
+    slli.w $r4,$r4,1
+    or     $r4,$r5,$r4
+    slli.w $r4,$r4,0    # <= redundant
+    jr	   $r1
+
+To eliminate this redundant extension we need to turn SImode shift etc.
+to DImode "si3_extend" operations earlier, when we expand the SImode
+operation.  We are already doing this for addition, now do it for
+shifts, rotates, substract, multiplication, division, and modulo as
+well.
+
+The bytepick.w definition for TARGET_64BIT needs to be adjusted so it
+won't be undone by the shift expanding.
+
+gcc/ChangeLog:
+
+	* config/loongarch/loongarch.md (optab): Add (rotatert "rotr").
+	(<optab:any_shift><mode>3, <optab:any_div><mode>3,
+	sub<mode>3, rotr<mode>3, mul<mode>3): Add a "*" to the insn name
+	so we can redefine the names with define_expand.
+	(*<optab:any_shift>si3_extend): Remove "*" so we can use them
+	in expanders.
+	(*subsi3_extended, *mulsi3_extended): Likewise, also remove the
+	trailing "ed" for consistency.
+	(*<optab:any_div>si3_extended): Add mode for sign_extend to
+	prevent an ICE using it in expanders.
+	(shift_w, arith_w): New define_code_iterator.
+	(<optab:any_w><mode>3): New define_expand.  Expand with
+	<optab:any_w>si3_extend for SImode if TARGET_64BIT.
+	(<optab:arith_w><mode>3): Likewise.
+	(mul<mode>3): Expand to mulsi3_extended for SImode if
+	TARGET_64BIT and ISA_HAS_DIV32.
+	(<optab:any_div><mode>3): Expand to <optab:any_div>si3_extended
+	for SImode if TARGET_64BIT.
+	(rotl<mode>3): Expand to rotrsi3_extend for SImode if
+	TARGET_64BIT.
+	(bytepick_w_<bytepick_imm>): Add mode for lshiftrt and ashift.
+	(bitsize, bytepick_imm, bytepick_w_ashift_amount): New
+	define_mode_attr.
+	(bytepick_w_<bytepick_imm>_extend): Adjust for the RTL change
+	caused by 32-bit shift expanding.  Now bytepick_imm only covers
+	2 and 3, separate one remaining case to ...
+	(bytepick_w_1_extend): ... here, new define_insn.
+
+gcc/testsuite/ChangeLog:
+
+	* gcc.target/loongarch/bitwise_extend.c: New test.
+---
+ gcc/config/loongarch/loongarch.md             | 131 +++++++++++++++---
+ .../gcc.target/loongarch/bitwise_extend.c     |  45 ++++++
+ 2 files changed, 154 insertions(+), 22 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/loongarch/bitwise_extend.c
+
+diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
+index 459ad30b9..9bad79bbf 100644
+--- a/gcc/config/loongarch/loongarch.md
++++ b/gcc/config/loongarch/loongarch.md
+@@ -546,6 +546,7 @@
+ (define_code_attr optab [(ashift "ashl")
+ 			 (ashiftrt "ashr")
+ 			 (lshiftrt "lshr")
++			 (rotatert "rotr")
+ 			 (ior "ior")
+ 			 (xor "xor")
+ 			 (and "and")
+@@ -624,6 +625,49 @@
+ 				 (48 "6")
+ 				 (56 "7")])
+ 
++;; Expand some 32-bit operations to si3_extend operations if TARGET_64BIT
++;; so the redundant sign extension can be removed if the output is used as
++;; an input of a bitwise operation.  Note plus, rotl, and div are handled
++;; separately.
++(define_code_iterator shift_w [any_shift rotatert])
++(define_code_iterator arith_w [minus mult])
++
++(define_expand "<optab><mode>3"
++  [(set (match_operand:GPR 0 "register_operand" "=r")
++	(shift_w:GPR (match_operand:GPR 1 "register_operand" "r")
++		     (match_operand:SI 2 "arith_operand" "rI")))]
++  ""
++{
++  if (TARGET_64BIT && <MODE>mode == SImode)
++    {
++      rtx t = gen_reg_rtx (DImode);
++      emit_insn (gen_<optab>si3_extend (t, operands[1], operands[2]));
++      t = gen_lowpart (SImode, t);
++      SUBREG_PROMOTED_VAR_P (t) = 1;
++      SUBREG_PROMOTED_SET (t, SRP_SIGNED);
++      emit_move_insn (operands[0], t);
++      DONE;
++    }
++})
++
++(define_expand "<optab><mode>3"
++  [(set (match_operand:GPR 0 "register_operand" "=r")
++	(arith_w:GPR (match_operand:GPR 1 "register_operand" "r")
++		     (match_operand:GPR 2 "register_operand" "r")))]
++  ""
++{
++  if (TARGET_64BIT && <MODE>mode == SImode)
++    {
++      rtx t = gen_reg_rtx (DImode);
++      emit_insn (gen_<optab>si3_extend (t, operands[1], operands[2]));
++      t = gen_lowpart (SImode, t);
++      SUBREG_PROMOTED_VAR_P (t) = 1;
++      SUBREG_PROMOTED_SET (t, SRP_SIGNED);
++      emit_move_insn (operands[0], t);
++      DONE;
++    }
++})
++
+ ;;
+ ;;  ....................
+ ;;
+@@ -781,7 +825,7 @@
+   [(set_attr "type" "fadd")
+    (set_attr "mode" "<UNITMODE>")])
+ 
+-(define_insn "sub<mode>3"
++(define_insn "*sub<mode>3"
+   [(set (match_operand:GPR 0 "register_operand" "=r")
+ 	(minus:GPR (match_operand:GPR 1 "register_operand" "r")
+ 		   (match_operand:GPR 2 "register_operand" "r")))]
+@@ -791,7 +835,7 @@
+    (set_attr "mode" "<MODE>")])
+ 
+ 
+-(define_insn "*subsi3_extended"
++(define_insn "subsi3_extend"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+ 	(sign_extend:DI
+ 	    (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
+@@ -818,7 +862,7 @@
+   [(set_attr "type" "fmul")
+    (set_attr "mode" "<MODE>")])
+ 
+-(define_insn "mul<mode>3"
++(define_insn "*mul<mode>3"
+   [(set (match_operand:GPR 0 "register_operand" "=r")
+ 	(mult:GPR (match_operand:GPR 1 "register_operand" "r")
+ 		  (match_operand:GPR 2 "register_operand" "r")))]
+@@ -827,7 +871,7 @@
+   [(set_attr "type" "imul")
+    (set_attr "mode" "<MODE>")])
+ 
+-(define_insn "*mulsi3_extended"
++(define_insn "mulsi3_extend"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+ 	(sign_extend:DI
+ 	    (mult:SI (match_operand:SI 1 "register_operand" "r")
+@@ -1001,8 +1045,19 @@
+ 		     (match_operand:GPR 2 "register_operand")))]
+   ""
+ {
+- if (GET_MODE (operands[0]) == SImode && TARGET_64BIT && !ISA_HAS_DIV32)
++ if (GET_MODE (operands[0]) == SImode && TARGET_64BIT)
+   {
++    if (ISA_HAS_DIV32)
++      {
++        rtx t = gen_reg_rtx (DImode);
++        emit_insn (gen_<optab>si3_extended (t, operands[1], operands[2]));
++        t = gen_lowpart (SImode, t);
++        SUBREG_PROMOTED_VAR_P (t) = 1;
++        SUBREG_PROMOTED_SET (t, SRP_SIGNED);
++        emit_move_insn (operands[0], t);
++        DONE;
++      }
++
+     rtx reg1 = gen_reg_rtx (DImode);
+     rtx reg2 = gen_reg_rtx (DImode);
+     rtx rd = gen_reg_rtx (DImode);
+@@ -1038,7 +1093,7 @@
+ 
+ (define_insn "<optab>si3_extended"
+   [(set (match_operand:DI 0 "register_operand" "=r,&r,&r")
+-	(sign_extend
++	(sign_extend:DI
+ 	  (any_div:SI (match_operand:SI 1 "register_operand" "r,r,0")
+ 		      (match_operand:SI 2 "register_operand" "r,r,r"))))]
+   "TARGET_64BIT && ISA_HAS_DIV32"
+@@ -2981,7 +3036,7 @@
+ ;;
+ ;;  ....................
+ 
+-(define_insn "<optab><mode>3"
++(define_insn "*<optab><mode>3"
+   [(set (match_operand:GPR 0 "register_operand" "=r")
+ 	(any_shift:GPR (match_operand:GPR 1 "register_operand" "r")
+ 		       (match_operand:SI 2 "arith_operand" "rI")))]
+@@ -2996,7 +3051,7 @@
+   [(set_attr "type" "shift")
+    (set_attr "mode" "<MODE>")])
+ 
+-(define_insn "*<optab>si3_extend"
++(define_insn "<optab>si3_extend"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+ 	(sign_extend:DI
+ 	   (any_shift:SI (match_operand:SI 1 "register_operand" "r")
+@@ -3011,7 +3066,7 @@
+   [(set_attr "type" "shift")
+    (set_attr "mode" "SI")])
+ 
+-(define_insn "rotr<mode>3"
++(define_insn "*rotr<mode>3"
+   [(set (match_operand:GPR 0 "register_operand" "=r,r")
+ 	(rotatert:GPR (match_operand:GPR 1 "register_operand" "r,r")
+ 		      (match_operand:SI 2 "arith_operand" "r,I")))]
+@@ -3040,6 +3095,19 @@
+   ""
+   {
+     operands[3] = gen_reg_rtx (SImode);
++
++    if (TARGET_64BIT && <MODE>mode == SImode)
++      {
++	rtx t = gen_reg_rtx (DImode);
++
++	emit_insn (gen_negsi2 (operands[3], operands[2]));
++	emit_insn (gen_rotrsi3_extend (t, operands[1], operands[3]));
++	t = gen_lowpart (SImode, t);
++	SUBREG_PROMOTED_VAR_P (t) = 1;
++	SUBREG_PROMOTED_SET (t, SRP_SIGNED);
++	emit_move_insn (operands[0], t);
++	DONE;
++      }
+   });
+ 
+ ;; The following templates were added to generate "bstrpick.d + alsl.d"
+@@ -4061,26 +4129,45 @@
+ 
+ (define_insn "bytepick_w_<bytepick_imm>"
+   [(set (match_operand:SI 0 "register_operand" "=r")
+-	(ior:SI (lshiftrt (match_operand:SI 1 "register_operand" "r")
+-			  (const_int <bytepick_w_lshiftrt_amount>))
+-		(ashift (match_operand:SI 2 "register_operand" "r")
+-			(const_int bytepick_w_ashift_amount))))]
++	(ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
++			     (const_int <bytepick_w_lshiftrt_amount>))
++		(ashift:SI (match_operand:SI 2 "register_operand" "r")
++			   (const_int bytepick_w_ashift_amount))))]
+   ""
+   "bytepick.w\t%0,%1,%2,<bytepick_imm>"
+   [(set_attr "mode" "SI")])
+ 
++(define_mode_attr bitsize [(QI "8") (HI "16")])
++(define_mode_attr bytepick_imm [(QI "3") (HI "2")])
++(define_mode_attr bytepick_w_ashift_amount [(QI "24") (HI "16")])
++
+ (define_insn "bytepick_w_<bytepick_imm>_extend"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+-	(sign_extend:DI
+-	 (subreg:SI
+-	  (ior:DI (subreg:DI (lshiftrt
+-			      (match_operand:SI 1 "register_operand" "r")
+-			      (const_int <bytepick_w_lshiftrt_amount>)) 0)
+-		  (subreg:DI (ashift
+-			      (match_operand:SI 2 "register_operand" "r")
+-			      (const_int bytepick_w_ashift_amount)) 0)) 0)))]
++	(ior:DI
++	  (ashift:DI
++	    (sign_extend:DI
++	      (subreg:SHORT (match_operand:DI 1 "register_operand" "r") 0))
++	    (const_int <bytepick_w_ashift_amount>))
++	  (zero_extract:DI (match_operand:DI 2 "register_operand" "r")
++			   (const_int <bytepick_w_ashift_amount>)
++			   (const_int <bitsize>))))]
+   "TARGET_64BIT"
+-  "bytepick.w\t%0,%1,%2,<bytepick_imm>"
++  "bytepick.w\t%0,%2,%1,<bytepick_imm>"
++  [(set_attr "mode" "SI")])
++
++(define_insn "bytepick_w_1_extend"
++  [(set (match_operand:DI 0 "register_operand" "=r")
++	(ior:DI
++	  (ashift:DI
++	    (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
++                         (const_int 24)
++                         (const_int 0))
++        (const_int 8))
++	  (zero_extract:DI (match_operand:DI 2 "register_operand" "r")
++			   (const_int 8)
++			   (const_int 24))))]
++  "TARGET_64BIT"
++  "bytepick.w\t%0,%2,%1,1"
+   [(set_attr "mode" "SI")])
+ 
+ (define_insn "bytepick_d_<bytepick_imm>"
+diff --git a/gcc/testsuite/gcc.target/loongarch/bitwise_extend.c b/gcc/testsuite/gcc.target/loongarch/bitwise_extend.c
+new file mode 100644
+index 000000000..c2bc489a7
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/loongarch/bitwise_extend.c
+@@ -0,0 +1,45 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=loongarch64 -mdiv32" } */
++/* { dg-final { scan-assembler-not "slli\\.w" } } */
++
++int
++f1 (int a, int b)
++{
++  return (a << b) | b;
++}
++
++int
++f2 (int a, int b)
++{
++  return (a - b) | b;
++}
++
++int
++f3 (int a, int b)
++{
++  return (a * b) | b;
++}
++
++int
++f4 (int a, int b)
++{
++  return (unsigned) a >> b | (unsigned) a << (32 - b) | b;
++}
++
++int
++f5 (int a, int b)
++{
++  return (unsigned) a << b | (unsigned) a >> (32 - b) | b;
++}
++
++int
++f6 (int a, int b)
++{
++  return (a % b) | b;
++}
++
++int
++f7 (int a, int b)
++{
++  return (a + b) | b;
++}
+-- 
+2.43.0
+

0011-LoongArch-Relax-ins_zero_bitmask_operand-and-remove-.patch

@@ -0,0 +1,123 @@
+From 6f1e77e40203e99258086c22d2079254d8b3402e Mon Sep 17 00:00:00 2001
+From: Xi Ruoyao <xry111@xry111.site>
+Date: Sun, 28 Jul 2024 17:02:49 +0800
+Subject: [PATCH 11/20] LoongArch: Relax ins_zero_bitmask_operand and remove
+ and<mode>3_align
+
+In r15-1207 I was too stupid to realize we just need to relax
+ins_zero_bitmask_operand to allow using bstrins for aligning, instead of
+adding a new split.  And, "> 12" in ins_zero_bitmask_operand also makes
+no sense: it rejects bstrins for things like "x & ~4l" with no good
+reason.
+
+So fix my errors now.
+
+gcc/ChangeLog:
+
+	* config/loongarch/predicates.md (ins_zero_bitmask_operand):
+	Cover more cases that bstrins can benefit.
+	(high_bitmask_operand): Remove.
+	* config/loongarch/constraints.md (Yy): Remove.
+	* config/loongarch/loongarch.md (and<mode>3_align): Remove.
+
+gcc/testsuite/ChangeLog:
+
+	* gcc.target/loongarch/bstrins-4.c: New test.
+---
+ gcc/config/loongarch/constraints.md            |  4 ----
+ gcc/config/loongarch/loongarch.md              | 17 -----------------
+ gcc/config/loongarch/predicates.md             |  9 ++-------
+ gcc/testsuite/gcc.target/loongarch/bstrins-4.c |  9 +++++++++
+ 4 files changed, 11 insertions(+), 28 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/loongarch/bstrins-4.c
+
+diff --git a/gcc/config/loongarch/constraints.md b/gcc/config/loongarch/constraints.md
+index 12cf5e292..18da8b31f 100644
+--- a/gcc/config/loongarch/constraints.md
++++ b/gcc/config/loongarch/constraints.md
+@@ -292,10 +292,6 @@
+    "@internal"
+    (match_operand 0 "low_bitmask_operand"))
+ 
+-(define_constraint "Yy"
+-   "@internal"
+-   (match_operand 0 "high_bitmask_operand"))
+-
+ (define_constraint "YI"
+   "@internal
+    A replicated vector const in which the replicated value is in the range
+diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
+index 9bad79bbf..280d1c403 100644
+--- a/gcc/config/loongarch/loongarch.md
++++ b/gcc/config/loongarch/loongarch.md
+@@ -1588,23 +1588,6 @@
+   [(set_attr "move_type" "pick_ins")
+    (set_attr "mode" "<MODE>")])
+ 
+-(define_insn_and_split "and<mode>3_align"
+-  [(set (match_operand:GPR 0 "register_operand" "=r")
+-	(and:GPR (match_operand:GPR 1 "register_operand" "r")
+-		 (match_operand:GPR 2 "high_bitmask_operand" "Yy")))]
+-  ""
+-  "#"
+-  ""
+-  [(set (match_dup 0) (match_dup 1))
+-   (set (zero_extract:GPR (match_dup 0) (match_dup 2) (const_int 0))
+-	(const_int 0))]
+-{
+-  int len;
+-
+-  len = low_bitmask_len (<MODE>mode, ~INTVAL (operands[2]));
+-  operands[2] = GEN_INT (len);
+-})
+-
+ (define_insn_and_split "*bstrins_<mode>_for_mask"
+   [(set (match_operand:GPR 0 "register_operand" "=r")
+ 	(and:GPR (match_operand:GPR 1 "register_operand" "r")
+diff --git a/gcc/config/loongarch/predicates.md b/gcc/config/loongarch/predicates.md
+index 58e406ea5..95c2544cc 100644
+--- a/gcc/config/loongarch/predicates.md
++++ b/gcc/config/loongarch/predicates.md
+@@ -293,10 +293,6 @@
+   (and (match_code "const_int")
+        (match_test "low_bitmask_len (mode, INTVAL (op)) > 12")))
+ 
+-(define_predicate "high_bitmask_operand"
+-  (and (match_code "const_int")
+-       (match_test "low_bitmask_len (mode, ~INTVAL (op)) > 0")))
+-
+ (define_predicate "d_operand"
+   (and (match_code "reg")
+        (match_test "GP_REG_P (REGNO (op))")))
+@@ -406,11 +402,10 @@
+ 
+ (define_predicate "ins_zero_bitmask_operand"
+   (and (match_code "const_int")
+-       (match_test "INTVAL (op) != -1")
+-       (match_test "INTVAL (op) & 1")
+        (match_test "low_bitmask_len (mode, \
+ 				     ~UINTVAL (op) | (~UINTVAL(op) - 1)) \
+-		    > 12")))
++		    > 0")
++       (not (match_operand 0 "const_uns_arith_operand"))))
+ 
+ (define_predicate "const_call_insn_operand"
+   (match_code "const,symbol_ref,label_ref")
+diff --git a/gcc/testsuite/gcc.target/loongarch/bstrins-4.c b/gcc/testsuite/gcc.target/loongarch/bstrins-4.c
+new file mode 100644
+index 000000000..0823cfc38
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/loongarch/bstrins-4.c
+@@ -0,0 +1,9 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */
++/* { dg-final { scan-assembler "bstrins\\.d\t\\\$r4,\\\$r0,2,2" } } */
++
++long
++x (long a)
++{
++  return a & ~4;
++}
+-- 
+2.43.0
+

0012-LoongArch-Rework-bswap-hi-si-di-2-definition.patch

@@ -0,0 +1,224 @@
+From 576f0886422697a97bb96d3abc43f6ef15f470c5 Mon Sep 17 00:00:00 2001
+From: Xi Ruoyao <xry111@xry111.site>
+Date: Sun, 28 Jul 2024 19:57:02 +0800
+Subject: [PATCH 12/20] LoongArch: Rework bswap{hi,si,di}2 definition
+
+Per a gcc-help thread we are generating sub-optimal code for
+__builtin_bswap{32,64}.  To fix it:
+
+- Use a single revb.d instruction for bswapdi2.
+- Use a single revb.2w instruction for bswapsi2 for TARGET_64BIT,
+  revb.2h + rotri.w for !TARGET_64BIT.
+- Use a single revb.2h instruction for bswapsi2 (x) r>> 16, and a single
+  revb.2w instruction for bswapdi2 (x) r>> 32.
+
+Unfortunately I cannot figure out a way to make the compiler generate
+revb.4h or revh.{2w,d} instructions.
+
+gcc/ChangeLog:
+
+	* config/loongarch/loongarch.md (UNSPEC_REVB_2H, UNSPEC_REVB_4H,
+	UNSPEC_REVH_D): Remove UNSPECs.
+	(revb_4h, revh_d): Remove define_insn.
+	(revb_2h): Define as (rotatert:SI (bswap:SI x) 16) instead of
+	an UNSPEC.
+	(revb_2h_extend, revb_2w, *bswapsi2, bswapdi2): New define_insn.
+	(bswapsi2): Change to define_expand.  Only expand to revb.2h +
+	rotri.w if !TARGET_64BIT.
+	(bswapdi2): Change to define_insn of which the output is just a
+	revb.d instruction.
+
+gcc/testsuite/ChangeLog:
+
+	* gcc.target/loongarch/revb.c: New test.
+---
+ gcc/config/loongarch/loongarch.md         | 79 ++++++++++++-----------
+ gcc/testsuite/gcc.target/loongarch/revb.c | 61 +++++++++++++++++
+ 2 files changed, 104 insertions(+), 36 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/loongarch/revb.c
+
+diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
+index 280d1c403..ee0310f2b 100644
+--- a/gcc/config/loongarch/loongarch.md
++++ b/gcc/config/loongarch/loongarch.md
+@@ -20,11 +20,6 @@
+ ;; <http://www.gnu.org/licenses/>.
+ 
+ (define_c_enum "unspec" [
+-  ;; Integer operations that are too cumbersome to describe directly.
+-  UNSPEC_REVB_2H
+-  UNSPEC_REVB_4H
+-  UNSPEC_REVH_D
+-
+   ;; Floating-point moves.
+   UNSPEC_LOAD_LOW
+   UNSPEC_LOAD_HIGH
+@@ -3151,55 +3146,67 @@
+ 
+ ;; Reverse the order of bytes of operand 1 and store the result in operand 0.
+ 
+-(define_insn "bswaphi2"
+-  [(set (match_operand:HI 0 "register_operand" "=r")
+-	(bswap:HI (match_operand:HI 1 "register_operand" "r")))]
++(define_insn "revb_2h"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(rotatert:SI (bswap:SI (match_operand:SI 1 "register_operand" "r"))
++		     (const_int 16)))]
+   ""
+   "revb.2h\t%0,%1"
+   [(set_attr "type" "shift")])
+ 
+-(define_insn_and_split "bswapsi2"
+-  [(set (match_operand:SI 0 "register_operand" "=r")
+-	(bswap:SI (match_operand:SI 1 "register_operand" "r")))]
+-  ""
+-  "#"
+-  ""
+-  [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_REVB_2H))
+-   (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))]
+-  ""
+-  [(set_attr "insn_count" "2")])
+-
+-(define_insn_and_split "bswapdi2"
++(define_insn "revb_2h_extend"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+-	(bswap:DI (match_operand:DI 1 "register_operand" "r")))]
++	(sign_extend:DI
++	  (rotatert:SI
++	    (bswap:SI (match_operand:SI 1 "register_operand" "r"))
++	    (const_int 16))))]
+   "TARGET_64BIT"
+-  "#"
+-  ""
+-  [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_REVB_4H))
+-   (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_REVH_D))]
+-  ""
+-  [(set_attr "insn_count" "2")])
++  "revb.2h\t%0,%1"
++  [(set_attr "type" "shift")])
+ 
+-(define_insn "revb_2h"
+-  [(set (match_operand:SI 0 "register_operand" "=r")
+-	(unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_REVB_2H))]
++(define_insn "bswaphi2"
++  [(set (match_operand:HI 0 "register_operand" "=r")
++	(bswap:HI (match_operand:HI 1 "register_operand" "r")))]
+   ""
+   "revb.2h\t%0,%1"
+   [(set_attr "type" "shift")])
+ 
+-(define_insn "revb_4h"
++(define_insn "revb_2w"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+-	(unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_REVB_4H))]
++	(rotatert:DI (bswap:DI (match_operand:DI 1 "register_operand" "r"))
++		     (const_int 32)))]
+   "TARGET_64BIT"
+-  "revb.4h\t%0,%1"
++  "revb.2w\t%0,%1"
+   [(set_attr "type" "shift")])
+ 
+-(define_insn "revh_d"
++(define_insn "*bswapsi2"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(bswap:SI (match_operand:SI 1 "register_operand" "r")))]
++  "TARGET_64BIT"
++  "revb.2w\t%0,%1"
++  [(set_attr "type" "shift")])
++
++(define_expand "bswapsi2"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(bswap:SI (match_operand:SI 1 "register_operand" "r")))]
++  ""
++{
++  if (!TARGET_64BIT)
++    {
++      rtx t = gen_reg_rtx (SImode);
++      emit_insn (gen_revb_2h (t, operands[1]));
++      emit_insn (gen_rotrsi3 (operands[0], t, GEN_INT (16)));
++      DONE;
++    }
++})
++
++(define_insn "bswapdi2"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+-	(unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_REVH_D))]
++	(bswap:DI (match_operand:DI 1 "register_operand" "r")))]
+   "TARGET_64BIT"
+-  "revh.d\t%0,%1"
++  "revb.d\t%0,%1"
+   [(set_attr "type" "shift")])
++
+ 
+ ;;
+ ;;  ....................
+diff --git a/gcc/testsuite/gcc.target/loongarch/revb.c b/gcc/testsuite/gcc.target/loongarch/revb.c
+new file mode 100644
+index 000000000..27a5d0fc7
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/loongarch/revb.c
+@@ -0,0 +1,61 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */
++/* { dg-final { check-function-bodies "**" "" } } */
++
++/*
++**t1:
++**	revb.2w	\$r4,\$r4
++**	slli.w	\$r4,\$r4,0
++**	jr	\$r1
++*/
++unsigned int
++t1 (unsigned int x)
++{
++  return __builtin_bswap32 (x);
++}
++
++/*
++**t2:
++**	revb.d	\$r4,\$r4
++**	jr	\$r1
++*/
++unsigned long
++t2 (unsigned long x)
++{
++  return __builtin_bswap64 (x);
++}
++
++/*
++**t3:
++**	revb.2h	\$r4,\$r4
++**	jr	\$r1
++*/
++unsigned int
++t3 (unsigned int x)
++{
++  return (x >> 8) & 0xff00ff | (x << 8) & 0xff00ff00;
++}
++
++/*
++**t4:
++**	revb.2w	\$r4,\$r4
++**	jr	\$r1
++*/
++unsigned long
++t4 (unsigned long x)
++{
++  x = __builtin_bswap64 (x);
++  return x << 32 | x >> 32;
++}
++
++/*
++**t5:
++**	revb.2h	\$r4,\$r4
++**	bstrpick.w	\$r4,\$r4,15,0
++**	jr	\$r1
++*/
++unsigned short
++t5 (unsigned short x)
++{
++  return __builtin_bswap16 (x);
++}
+-- 
+2.43.0
+

0013-testsuite-fix-dg-do-preprocess-typo.patch

@@ -0,0 +1,26 @@
+From a12e2e758da5307440b483b74e3ddeff5317c4e7 Mon Sep 17 00:00:00 2001
+From: Sam James <sam@gentoo.org>
+Date: Tue, 30 Jul 2024 21:46:29 +0100
+Subject: [PATCH 13/20] testsuite: fix 'dg-do-preprocess' typo
+
+We want 'dg-do preprocess', not 'dg-do-preprocess'. Fix that.
+
+	PR target/106828
+	* g++.target/loongarch/pr106828.C: Fix 'dg-do compile' typo.
+---
+ gcc/testsuite/g++.target/loongarch/pr106828.C | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/testsuite/g++.target/loongarch/pr106828.C b/gcc/testsuite/g++.target/loongarch/pr106828.C
+index 190c1db71..0d13cbbd5 100644
+--- a/gcc/testsuite/g++.target/loongarch/pr106828.C
++++ b/gcc/testsuite/g++.target/loongarch/pr106828.C
+@@ -1,4 +1,4 @@
+-/* { dg-do-preprocess } */
++/* { dg-do preprocess } */
+ /* { dg-options "-mabi=lp64d -fsanitize=address" } */
+ 
+ /* Tests whether the compiler supports compile option '-fsanitize=address'.  */
+-- 
+2.43.0
+

0014-LoongArch-Remove-gawk-extension-from-a-generator-scr.patch

@@ -0,0 +1,47 @@
+From 3b95d64e62dc1884da153f37a14753c3a74751e8 Mon Sep 17 00:00:00 2001
+From: Yang Yujie <yangyujie@loongson.cn>
+Date: Tue, 23 Jul 2024 10:04:26 +0800
+Subject: [PATCH 14/20] LoongArch: Remove gawk extension from a generator
+ script.
+
+gcc/ChangeLog:
+
+	* config/loongarch/genopts/gen-evolution.awk: Do not use
+	"length()" to compute the size of an array.
+---
+ gcc/config/loongarch/genopts/gen-evolution.awk | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/loongarch/genopts/gen-evolution.awk b/gcc/config/loongarch/genopts/gen-evolution.awk
+index 4d105afa9..1c8004e41 100644
+--- a/gcc/config/loongarch/genopts/gen-evolution.awk
++++ b/gcc/config/loongarch/genopts/gen-evolution.awk
+@@ -1,4 +1,4 @@
+-#!/usr/bin/gawk
++#!/usr/bin/awk -f
+ #
+ # A simple script that generates loongarch-evolution.h
+ # from genopts/isa-evolution.in
+@@ -94,8 +94,9 @@ function gen_cpucfg_useful_idx()
+         idx_bucket[cpucfg_word[i]] = 1
+ 
+     delete idx_list
++    j = 1
+     for (i in idx_bucket)
+-        idx_list[length(idx_list)-1] = i+0
++        idx_list[j++] = i+0
+     delete idx_bucket
+ 
+     asort (idx_list)
+@@ -108,7 +109,7 @@ function gen_cpucfg_useful_idx()
+     print ""
+ 
+     printf ("static constexpr int N_CPUCFG_WORDS = %d;\n",
+-            idx_list[length(idx_list)] + 1)
++            idx_list[j - 1] + 1)
+ 
+     delete idx_list
+ }
+-- 
+2.43.0
+

0015-LoongArch-Use-iorn-and-andn-standard-pattern-names.patch

@@ -0,0 +1,226 @@
+From 4fccfea59b4924e9218dc0cb13093d26995dd6b4 Mon Sep 17 00:00:00 2001
+From: Lulu Cheng <chenglulu@loongson.cn>
+Date: Thu, 1 Aug 2024 16:07:25 +0800
+Subject: [PATCH 15/20] LoongArch: Use iorn and andn standard pattern names.
+
+R15-1890 introduced new optabs iorc and andc, and its corresponding
+internal functions BIT_{ANDC,IORC}, and if targets defines such optabs
+for vector modes.  And in r15-2258 the iorc and andc were renamed to
+iorn and andn.
+So we changed the andn and iorn implementation templates to the standard
+template names.
+
+gcc/ChangeLog:
+
+	* config/loongarch/lasx.md (xvandn<mode>3): Rename to ...
+	(andn<mode>3): This.
+	(xvorn<mode>3): Rename to ...
+	(iorn<mode>3): This.
+	* config/loongarch/loongarch-builtins.cc
+	(CODE_FOR_lsx_vandn_v): Defined as the modified name.
+	(CODE_FOR_lsx_vorn_v): Likewise.
+	(CODE_FOR_lasx_xvandn_v): Likewise.
+	(CODE_FOR_lasx_xvorn_v): Likewise.
+	(loongarch_expand_builtin_insn): When the builtin function to be
+	called is __builtin_lasx_xvandn or __builtin_lsx_vandn, swap the
+	two operands.
+	* config/loongarch/loongarch.md (<optab>n<mode>): Rename to ...
+	(<optab>n<mode>3): This.
+	* config/loongarch/lsx.md (vandn<mode>3): Rename to ...
+	(andn<mode>3): This.
+	(vorn<mode>3): Rename to ...
+	(iorn<mode>3): This.
+
+gcc/testsuite/ChangeLog:
+
+	* gcc.target/loongarch/lasx-andn-iorn.c: New test.
+	* gcc.target/loongarch/lsx-andn-iorn.c: New test.
+---
+ gcc/config/loongarch/lasx.md                  | 10 +++----
+ gcc/config/loongarch/loongarch-builtins.cc    | 10 ++++---
+ gcc/config/loongarch/loongarch.md             |  8 +++---
+ gcc/config/loongarch/lsx.md                   | 10 +++----
+ .../gcc.target/loongarch/lasx-andn-iorn.c     | 11 ++++++++
+ .../gcc.target/loongarch/lsx-andn-iorn.c      | 28 +++++++++++++++++++
+ 6 files changed, 59 insertions(+), 18 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/loongarch/lasx-andn-iorn.c
+ create mode 100644 gcc/testsuite/gcc.target/loongarch/lsx-andn-iorn.c
+
+diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
+index 7bd61f8ed..ca5238806 100644
+--- a/gcc/config/loongarch/lasx.md
++++ b/gcc/config/loongarch/lasx.md
+@@ -2716,12 +2716,12 @@
+    (set_attr "mode" "V4DI")])
+ 
+ ;; Extend loongson-sx to loongson-asx.
+-(define_insn "xvandn<mode>3"
++(define_insn "andn<mode>3"
+   [(set (match_operand:LASX 0 "register_operand" "=f")
+-	(and:LASX (not:LASX (match_operand:LASX 1 "register_operand" "f"))
+-			    (match_operand:LASX 2 "register_operand" "f")))]
++	(and:LASX (not:LASX (match_operand:LASX 2 "register_operand" "f"))
++			    (match_operand:LASX 1 "register_operand" "f")))]
+   "ISA_HAS_LASX"
+-  "xvandn.v\t%u0,%u1,%u2"
++  "xvandn.v\t%u0,%u2,%u1"
+   [(set_attr "type" "simd_logic")
+    (set_attr "mode" "<MODE>")])
+ 
+@@ -4637,7 +4637,7 @@
+   [(set_attr "type" "simd_int_arith")
+    (set_attr "mode" "<MODE>")])
+ 
+-(define_insn "xvorn<mode>3"
++(define_insn "iorn<mode>3"
+   [(set (match_operand:ILASX 0 "register_operand" "=f")
+ 	(ior:ILASX (not:ILASX (match_operand:ILASX 2 "register_operand" "f"))
+ 		   (match_operand:ILASX 1 "register_operand" "f")))]
+diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc
+index fbe46833c..cf92770de 100644
+--- a/gcc/config/loongarch/loongarch-builtins.cc
++++ b/gcc/config/loongarch/loongarch-builtins.cc
+@@ -458,8 +458,8 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE)
+ #define CODE_FOR_lsx_vabsd_du CODE_FOR_lsx_vabsd_u_du
+ #define CODE_FOR_lsx_vftint_wu_s CODE_FOR_lsx_vftint_u_wu_s
+ #define CODE_FOR_lsx_vftint_lu_d CODE_FOR_lsx_vftint_u_lu_d
+-#define CODE_FOR_lsx_vandn_v CODE_FOR_vandnv16qi3
+-#define CODE_FOR_lsx_vorn_v CODE_FOR_vornv16qi3
++#define CODE_FOR_lsx_vandn_v CODE_FOR_andnv16qi3
++#define CODE_FOR_lsx_vorn_v CODE_FOR_iornv16qi3
+ #define CODE_FOR_lsx_vneg_b CODE_FOR_vnegv16qi2
+ #define CODE_FOR_lsx_vneg_h CODE_FOR_vnegv8hi2
+ #define CODE_FOR_lsx_vneg_w CODE_FOR_vnegv4si2
+@@ -692,8 +692,8 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE)
+ #define CODE_FOR_lasx_xvrepli_w CODE_FOR_lasx_xvrepliv8si
+ #define CODE_FOR_lasx_xvrepli_d CODE_FOR_lasx_xvrepliv4di
+ 
+-#define CODE_FOR_lasx_xvandn_v CODE_FOR_xvandnv32qi3
+-#define CODE_FOR_lasx_xvorn_v CODE_FOR_xvornv32qi3
++#define CODE_FOR_lasx_xvandn_v CODE_FOR_andnv32qi3
++#define CODE_FOR_lasx_xvorn_v CODE_FOR_iornv32qi3
+ #define CODE_FOR_lasx_xvneg_b CODE_FOR_negv32qi2
+ #define CODE_FOR_lasx_xvneg_h CODE_FOR_negv16hi2
+ #define CODE_FOR_lasx_xvneg_w CODE_FOR_negv8si2
+@@ -2858,6 +2858,7 @@ loongarch_expand_builtin_insn (enum insn_code icode, unsigned int nops,
+     case CODE_FOR_lsx_vpickod_b:
+     case CODE_FOR_lsx_vpickod_h:
+     case CODE_FOR_lsx_vpickod_w:
++    case CODE_FOR_lsx_vandn_v:
+     case CODE_FOR_lasx_xvilvh_b:
+     case CODE_FOR_lasx_xvilvh_h:
+     case CODE_FOR_lasx_xvilvh_w:
+@@ -2878,6 +2879,7 @@ loongarch_expand_builtin_insn (enum insn_code icode, unsigned int nops,
+     case CODE_FOR_lasx_xvpickod_b:
+     case CODE_FOR_lasx_xvpickod_h:
+     case CODE_FOR_lasx_xvpickod_w:
++    case CODE_FOR_lasx_xvandn_v:
+       /* Swap the operands 1 and 2 for interleave operations.  Built-ins follow
+ 	 convention of ISA, which have op1 as higher component and op2 as lower
+ 	 component.  However, the VEC_PERM op in tree and vec_concat in RTL
+diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
+index ee0310f2b..261cb7d9d 100644
+--- a/gcc/config/loongarch/loongarch.md
++++ b/gcc/config/loongarch/loongarch.md
+@@ -1701,13 +1701,13 @@
+   [(set_attr "type" "logical")
+    (set_attr "mode" "SI")])
+ 
+-(define_insn "<optab>n<mode>"
++(define_insn "<optab>n<mode>3"
+   [(set (match_operand:X 0 "register_operand" "=r")
+ 	(neg_bitwise:X
+-	    (not:X (match_operand:X 1 "register_operand" "r"))
+-	    (match_operand:X 2 "register_operand" "r")))]
++	    (not:X (match_operand:X 2 "register_operand" "r"))
++	    (match_operand:X 1 "register_operand" "r")))]
+   ""
+-  "<insn>n\t%0,%2,%1"
++  "<insn>n\t%0,%1,%2"
+   [(set_attr "type" "logical")
+    (set_attr "mode" "<MODE>")])
+ 
+diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
+index 454cda478..6bdf4fe43 100644
+--- a/gcc/config/loongarch/lsx.md
++++ b/gcc/config/loongarch/lsx.md
+@@ -2344,12 +2344,12 @@
+ }
+   [(set_attr "mode" "V4SF")])
+ 
+-(define_insn "vandn<mode>3"
++(define_insn "andn<mode>3"
+   [(set (match_operand:LSX 0 "register_operand" "=f")
+-	(and:LSX (not:LSX (match_operand:LSX 1 "register_operand" "f"))
+-		 (match_operand:LSX 2 "register_operand" "f")))]
++	(and:LSX (not:LSX (match_operand:LSX 2 "register_operand" "f"))
++		 (match_operand:LSX 1 "register_operand" "f")))]
+   "ISA_HAS_LSX"
+-  "vandn.v\t%w0,%w1,%w2"
++  "vandn.v\t%w0,%w2,%w1"
+   [(set_attr "type" "simd_logic")
+    (set_attr "mode" "<MODE>")])
+ 
+@@ -3028,7 +3028,7 @@
+   [(set_attr "type" "simd_int_arith")
+    (set_attr "mode" "<MODE>")])
+ 
+-(define_insn "vorn<mode>3"
++(define_insn "iorn<mode>3"
+   [(set (match_operand:ILSX 0 "register_operand" "=f")
+ 	(ior:ILSX (not:ILSX (match_operand:ILSX 2 "register_operand" "f"))
+ 		  (match_operand:ILSX 1 "register_operand" "f")))]
+diff --git a/gcc/testsuite/gcc.target/loongarch/lasx-andn-iorn.c b/gcc/testsuite/gcc.target/loongarch/lasx-andn-iorn.c
+new file mode 100644
+index 000000000..4aa5f19a6
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/loongarch/lasx-andn-iorn.c
+@@ -0,0 +1,11 @@
++#define N 8
++
++#include "./lsx-andn-iorn.c"
++
++/* { dg-do compile } */
++/* { dg-options "-O2 -mlasx -ftree-vectorize" } */
++
++/* We should produce a BIT_ANDC and BIT_IORC here.  */
++
++/* { dg-final { scan-tree-dump ".BIT_ANDN " "optimized" } } */
++/* { dg-final { scan-tree-dump ".BIT_IORN " "optimized" } } */
+diff --git a/gcc/testsuite/gcc.target/loongarch/lsx-andn-iorn.c b/gcc/testsuite/gcc.target/loongarch/lsx-andn-iorn.c
+new file mode 100644
+index 000000000..7bceccd37
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/loongarch/lsx-andn-iorn.c
+@@ -0,0 +1,28 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mlsx -ftree-vectorize" } */
++
++#ifndef N
++#define N 4
++#endif
++
++extern float a[N], b[N];
++extern int c[N], d[N];
++
++void
++bar1 (void)
++{
++  for (int i = 0; i < N; i++)
++    d[i] = a[i] > b[i] ? 0 : c[i];
++}
++
++void
++bar2 (void)
++{
++  for (int i = 0; i < N; i++)
++    d[i] = a[i] > b[i] ? c[i]: -1;
++}
++
++/* We should produce a BIT_ANDC and BIT_IORC here.  */
++
++/* { dg-final { scan-tree-dump ".BIT_ANDN " "optimized" } } */
++/* { dg-final { scan-tree-dump ".BIT_IORN " "optimized" } } */
+-- 
+2.43.0
+

0016-LoongArch-Drop-vcond-u-expanders.patch

@@ -0,0 +1,127 @@
+From 3e2a8ca412a30756b1b2883a962e61e45a9ed5f6 Mon Sep 17 00:00:00 2001
+From: Lulu Cheng <chenglulu@loongson.cn>
+Date: Thu, 8 Aug 2024 10:39:54 +0800
+Subject: [PATCH 16/20] LoongArch: Drop vcond{,u} expanders.
+
+Optabs vcond{,u} will be removed for GCC 15.  Since regtest shows no
+fallout, dropping the expanders, now.
+
+gcc/ChangeLog:
+
+	PR target/114189
+	* config/loongarch/lasx.md (vcondu<LASX:mode><ILASX:mode>): Delete.
+	(vcond<LASX:mode><LASX_2:mode>): Likewise.
+	* config/loongarch/lsx.md (vcondu<LSX:mode><ILSX:mode>): Likewise.
+	(vcond<LSX:mode><LSX_2:mode>): Likewise.
+---
+ gcc/config/loongarch/lasx.md | 37 ------------------------------------
+ gcc/config/loongarch/lsx.md  | 31 ------------------------------
+ 2 files changed, 68 deletions(-)
+
+diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
+index ca5238806..d37b2e83c 100644
+--- a/gcc/config/loongarch/lasx.md
++++ b/gcc/config/loongarch/lasx.md
+@@ -165,9 +165,6 @@
+ ;; All vector modes with 256 bits.
+ (define_mode_iterator LASX [V4DF V8SF V4DI V8SI V16HI V32QI])
+ 
+-;; Same as LASX.  Used by vcond to iterate two modes.
+-(define_mode_iterator LASX_2 [V4DF V8SF V4DI V8SI V16HI V32QI])
+-
+ ;; Only used for splitting insert_d and copy_{u,s}.d.
+ (define_mode_iterator LASX_D [V4DI V4DF])
+ 
+@@ -762,40 +759,6 @@
+    DONE;
+ })
+ 
+-;; FIXME: 256??
+-(define_expand "vcondu<LASX:mode><ILASX:mode>"
+-  [(match_operand:LASX 0 "register_operand")
+-   (match_operand:LASX 1 "reg_or_m1_operand")
+-   (match_operand:LASX 2 "reg_or_0_operand")
+-   (match_operator 3 ""
+-    [(match_operand:ILASX 4 "register_operand")
+-     (match_operand:ILASX 5 "register_operand")])]
+-  "ISA_HAS_LASX
+-   && (GET_MODE_NUNITS (<LASX:MODE>mode)
+-       == GET_MODE_NUNITS (<ILASX:MODE>mode))"
+-{
+-  loongarch_expand_vec_cond_expr (<LASX:MODE>mode, <LASX:VIMODE256>mode,
+-				  operands);
+-  DONE;
+-})
+-
+-;; FIXME: 256??
+-(define_expand "vcond<LASX:mode><LASX_2:mode>"
+-  [(match_operand:LASX 0 "register_operand")
+-   (match_operand:LASX 1 "reg_or_m1_operand")
+-   (match_operand:LASX 2 "reg_or_0_operand")
+-   (match_operator 3 ""
+-     [(match_operand:LASX_2 4 "register_operand")
+-      (match_operand:LASX_2 5 "register_operand")])]
+-  "ISA_HAS_LASX
+-   && (GET_MODE_NUNITS (<LASX:MODE>mode)
+-       == GET_MODE_NUNITS (<LASX_2:MODE>mode))"
+-{
+-  loongarch_expand_vec_cond_expr (<LASX:MODE>mode, <LASX:VIMODE256>mode,
+-				  operands);
+-  DONE;
+-})
+-
+ ;; Same as vcond_
+ (define_expand "vcond_mask_<mode><mode256_i>"
+   [(match_operand:LASX 0 "register_operand")
+diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
+index 6bdf4fe43..fcba28b07 100644
+--- a/gcc/config/loongarch/lsx.md
++++ b/gcc/config/loongarch/lsx.md
+@@ -186,9 +186,6 @@
+ ;; All vector modes with 128 bits.
+ (define_mode_iterator LSX      [V2DF V4SF V2DI V4SI V8HI V16QI])
+ 
+-;; Same as LSX.  Used by vcond to iterate two modes.
+-(define_mode_iterator LSX_2    [V2DF V4SF V2DI V4SI V8HI V16QI])
+-
+ ;; Only used for vilvh and splitting insert_d and copy_{u,s}.d.
+ (define_mode_iterator LSX_D    [V2DI V2DF])
+ 
+@@ -533,34 +530,6 @@
+   DONE;
+ })
+ 
+-(define_expand "vcondu<LSX:mode><ILSX:mode>"
+-  [(match_operand:LSX 0 "register_operand")
+-   (match_operand:LSX 1 "reg_or_m1_operand")
+-   (match_operand:LSX 2 "reg_or_0_operand")
+-   (match_operator 3 ""
+-     [(match_operand:ILSX 4 "register_operand")
+-      (match_operand:ILSX 5 "register_operand")])]
+-  "ISA_HAS_LSX
+-   && (GET_MODE_NUNITS (<LSX:MODE>mode) == GET_MODE_NUNITS (<ILSX:MODE>mode))"
+-{
+-  loongarch_expand_vec_cond_expr (<LSX:MODE>mode, <LSX:VIMODE>mode, operands);
+-  DONE;
+-})
+-
+-(define_expand "vcond<LSX:mode><LSX_2:mode>"
+-  [(match_operand:LSX 0 "register_operand")
+-   (match_operand:LSX 1 "reg_or_m1_operand")
+-   (match_operand:LSX 2 "reg_or_0_operand")
+-   (match_operator 3 ""
+-     [(match_operand:LSX_2 4 "register_operand")
+-      (match_operand:LSX_2 5 "register_operand")])]
+-  "ISA_HAS_LSX
+-   && (GET_MODE_NUNITS (<LSX:MODE>mode) == GET_MODE_NUNITS (<LSX_2:MODE>mode))"
+-{
+-  loongarch_expand_vec_cond_expr (<LSX:MODE>mode, <LSX:VIMODE>mode, operands);
+-  DONE;
+-})
+-
+ (define_expand "vcond_mask_<mode><mode_i>"
+   [(match_operand:LSX 0 "register_operand")
+    (match_operand:LSX 1 "reg_or_m1_operand")
+-- 
+2.43.0
+

0017-LoongArch-Provide-ashr-lshr-and-ashl-RTL-pattern-for.patch

@@ -0,0 +1,220 @@
+From 41ff0f0c55e43ea0ab6f3f588a9193c56b217388 Mon Sep 17 00:00:00 2001
+From: Lulu Cheng <chenglulu@loongson.cn>
+Date: Thu, 8 Aug 2024 09:59:28 +0800
+Subject: [PATCH 17/20] LoongArch: Provide ashr lshr and ashl RTL pattern for
+ vectors.
+
+We support vashr vlshr and vashl. However, in r15-1638 support optimize
+x < 0 ? -1 : 0 into (signed) x >> 31 and x < 0 ? 1 : 0 into (unsigned) x >> 31.
+To support this optimization, vector ashr lshr and ashl need to be implemented.
+
+gcc/ChangeLog:
+
+	* config/loongarch/loongarch.md (insn): Added rotatert rotr pairs.
+	* config/loongarch/simd.md (rotr<mode>3): Remove to ...
+	(<optab><mode>3): This.
+
+gcc/testsuite/ChangeLog:
+
+	* g++.target/loongarch/vect-ashr-lshr.C: New test.
+---
+ gcc/config/loongarch/loongarch.md             |   1 +
+ gcc/config/loongarch/simd.md                  |  13 +-
+ .../g++.target/loongarch/vect-ashr-lshr.C     | 147 ++++++++++++++++++
+ 3 files changed, 155 insertions(+), 6 deletions(-)
+ create mode 100644 gcc/testsuite/g++.target/loongarch/vect-ashr-lshr.C
+
+diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
+index 261cb7d9d..73cdb38a4 100644
+--- a/gcc/config/loongarch/loongarch.md
++++ b/gcc/config/loongarch/loongarch.md
+@@ -559,6 +559,7 @@
+ (define_code_attr insn [(ashift "sll")
+ 			(ashiftrt "sra")
+ 			(lshiftrt "srl")
++			(rotatert "rotr")
+ 			(ior "or")
+ 			(xor "xor")
+ 			(and "and")
+diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md
+index 00ff2823a..45ea11422 100644
+--- a/gcc/config/loongarch/simd.md
++++ b/gcc/config/loongarch/simd.md
+@@ -306,14 +306,15 @@
+     operands[4] = gen_reg_rtx (<MODE>mode);
+   });
+ 
+-;; <x>vrotri.{b/h/w/d}
++;; <x>v{rotr/sll/sra/srl}i.{b/h/w/d}
+ 
+-(define_insn "rotr<mode>3"
++(define_insn "<optab><mode>3"
+   [(set (match_operand:IVEC 0 "register_operand" "=f")
+-	(rotatert:IVEC (match_operand:IVEC 1 "register_operand" "f")
+-		       (match_operand:SI 2 "const_<bitimm>_operand")))]
+-  ""
+-  "<x>vrotri.<simdfmt>\t%<wu>0,%<wu>1,%2";
++	(shift_w:IVEC
++	  (match_operand:IVEC 1 "register_operand" "f")
++	  (match_operand:SI 2 "const_<bitimm>_operand")))]
++  "ISA_HAS_LSX"
++  "<x>v<insn>i.<simdfmt>\t%<wu>0,%<wu>1,%2"
+   [(set_attr "type" "simd_int_arith")
+    (set_attr "mode" "<MODE>")])
+ 
+diff --git a/gcc/testsuite/g++.target/loongarch/vect-ashr-lshr.C b/gcc/testsuite/g++.target/loongarch/vect-ashr-lshr.C
+new file mode 100644
+index 000000000..bcef985fa
+--- /dev/null
++++ b/gcc/testsuite/g++.target/loongarch/vect-ashr-lshr.C
+@@ -0,0 +1,147 @@
++/* { dg-do compile } */
++/* { dg-options "-mlasx -O2" } */
++/* { dg-final { scan-assembler-times "vsrli.b" 2 } } */
++/* { dg-final { scan-assembler-times "vsrli.h" 2 } } */
++/* { dg-final { scan-assembler-times "vsrli.w" 2 } } */
++/* { dg-final { scan-assembler-times "vsrli.d" 2 } } */
++/* { dg-final { scan-assembler-times "vsrai.b" 2 } } */
++/* { dg-final { scan-assembler-times "vsrai.h" 2 } } */
++/* { dg-final { scan-assembler-times "vsrai.w" 2 } } */
++/* { dg-final { scan-assembler-times "vsrai.d" 2 } } */
++
++typedef signed char v16qi __attribute__((vector_size(16)));
++typedef signed char v32qi __attribute__((vector_size(32)));
++typedef short v8hi __attribute__((vector_size(16)));
++typedef short v16hi __attribute__((vector_size(32)));
++typedef int v4si __attribute__((vector_size(16)));
++typedef int v8si __attribute__((vector_size(32)));
++typedef long long v2di __attribute__((vector_size(16)));
++typedef long long v4di __attribute__((vector_size(32)));
++
++v16qi
++foo (v16qi a)
++{
++  v16qi const1_op = __extension__(v16qi){1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};
++  v16qi const0_op = __extension__(v16qi){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
++  return a < const0_op ? const1_op : const0_op;
++}
++
++v32qi
++foo2 (v32qi a)
++{
++  v32qi const1_op = __extension__(v32qi){1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};
++  v32qi const0_op = __extension__(v32qi){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
++  return a < const0_op ? const1_op : const0_op;
++}
++
++v8hi
++foo3 (v8hi a)
++{
++  v8hi const1_op = __extension__(v8hi){1,1,1,1,1,1,1,1};
++  v8hi const0_op = __extension__(v8hi){0,0,0,0,0,0,0,0};
++  return a < const0_op ? const1_op : const0_op;
++}
++
++v16hi
++foo4 (v16hi a)
++{
++  v16hi const1_op = __extension__(v16hi){1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};
++  v16hi const0_op = __extension__(v16hi){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
++  return a < const0_op ? const1_op : const0_op;
++}
++
++v4si
++foo5 (v4si a)
++{
++  v4si const1_op = __extension__(v4si){1,1,1,1};
++  v4si const0_op = __extension__(v4si){0,0,0,0};
++  return a < const0_op ? const1_op : const0_op;
++}
++
++v8si
++foo6 (v8si a)
++{
++  v8si const1_op = __extension__(v8si){1,1,1,1,1,1,1,1};
++  v8si const0_op = __extension__(v8si){0,0,0,0,0,0,0,0};
++  return a < const0_op ? const1_op : const0_op;
++}
++
++v2di
++foo7 (v2di a)
++{
++  v2di const1_op = __extension__(v2di){1,1};
++  v2di const0_op = __extension__(v2di){0,0};
++  return a < const0_op ? const1_op : const0_op;
++}
++
++v4di
++foo8 (v4di a)
++{
++  v4di const1_op = __extension__(v4di){1,1,1,1};
++  v4di const0_op = __extension__(v4di){0,0,0,0};
++  return a < const0_op ? const1_op : const0_op;
++}
++
++v16qi
++foo9 (v16qi a)
++{
++  v16qi const1_op = __extension__(v16qi){-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1};
++  v16qi const0_op = __extension__(v16qi){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
++  return a < const0_op ? const1_op : const0_op;
++}
++
++v32qi
++foo10 (v32qi a)
++{
++  v32qi const1_op = __extension__(v32qi){-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1};
++  v32qi const0_op = __extension__(v32qi){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
++  return a < const0_op ? const1_op : const0_op;
++}
++
++v8hi
++foo11 (v8hi a)
++{
++  v8hi const1_op = __extension__(v8hi){-1,-1,-1,-1,-1,-1,-1,-1};
++  v8hi const0_op = __extension__(v8hi){0,0,0,0,0,0,0,0};
++  return a < const0_op ? const1_op : const0_op;
++}
++
++v16hi
++foo12 (v16hi a)
++{
++  v16hi const1_op = __extension__(v16hi){-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1};
++  v16hi const0_op = __extension__(v16hi){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
++  return a < const0_op ? const1_op : const0_op;
++}
++
++v4si
++foo13 (v4si a)
++{
++  v4si const1_op = __extension__(v4si){-1,-1,-1,-1};
++  v4si const0_op = __extension__(v4si){0,0,0,0};
++  return a < const0_op ? const1_op : const0_op;
++}
++
++v8si
++foo14 (v8si a)
++{
++  v8si const1_op = __extension__(v8si){-1,-1,-1,-1,-1,-1,-1,-1};
++  v8si const0_op = __extension__(v8si){0,0,0,0,0,0,0,0};
++  return a < const0_op ? const1_op : const0_op;
++}
++
++v2di
++foo15 (v2di a)
++{
++  v2di const1_op = __extension__(v2di){-1,-1};
++  v2di const0_op = __extension__(v2di){0,0};
++  return a < const0_op ? const1_op : const0_op;
++}
++
++v4di
++foo16 (v4di a)
++{
++  v4di const1_op = __extension__(v4di){-1,-1,-1,-1};
++  v4di const0_op = __extension__(v4di){0,0,0,0};
++  return a < const0_op ? const1_op : const0_op;
++}
+-- 
+2.43.0
+

0018-LoongArch-Implement-scalar-isinf-isnormal-and-isfini.patch

@@ -0,0 +1,203 @@
+From 1d08e8d3041c102154001b1813ca13e4886048eb Mon Sep 17 00:00:00 2001
+From: Xi Ruoyao <xry111@xry111.site>
+Date: Thu, 4 Jul 2024 02:49:28 +0800
+Subject: [PATCH 18/20] LoongArch: Implement scalar isinf, isnormal, and
+ isfinite via fclass
+
+Doing so can avoid loading FP constants from the memory.  It also
+partially fixes PR 66262 as fclass does not signal on sNaN.
+
+gcc/ChangeLog:
+
+	* config/loongarch/loongarch.md (extendsidi2): Add ("=r", "f")
+	alternative and use movfr2gr.s for it.  The spec clearly states
+	movfr2gr.s sign extends the value to GRLEN.
+	(fclass_<fmt>): Make the result SImode instead of a floating
+	mode.  The fclass results are really not FP values.
+	(FCLASS_MASK): New define_int_iterator.
+	(fclass_optab): New define_int_attr.
+	(<FCLASS_MASK:fclass_optab><ANYF:mode>): New define_expand
+	template.
+
+gcc/testsuite/ChangeLog:
+
+	* gcc.target/loongarch/fclass-compile.c: New test.
+	* gcc.target/loongarch/fclass-run.c: New test.
+---
+ gcc/config/loongarch/loongarch.md             | 53 ++++++++++++++++---
+ .../gcc.target/loongarch/fclass-compile.c     | 20 +++++++
+ .../gcc.target/loongarch/fclass-run.c         | 53 +++++++++++++++++++
+ 3 files changed, 119 insertions(+), 7 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/loongarch/fclass-compile.c
+ create mode 100644 gcc/testsuite/gcc.target/loongarch/fclass-run.c
+
+diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
+index 73cdb38a4..f70ca85bf 100644
+--- a/gcc/config/loongarch/loongarch.md
++++ b/gcc/config/loongarch/loongarch.md
+@@ -1851,16 +1851,17 @@
+ ;;  ....................
+ 
+ (define_insn "extendsidi2"
+-  [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
++  [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
+ 	(sign_extend:DI
+-	    (match_operand:SI 1 "nonimmediate_operand" "r,ZC,m,k")))]
++	    (match_operand:SI 1 "nonimmediate_operand" "r,ZC,m,k,f")))]
+   "TARGET_64BIT"
+   "@
+    slli.w\t%0,%1,0
+    ldptr.w\t%0,%1
+    ld.w\t%0,%1
+-   ldx.w\t%0,%1"
+-  [(set_attr "move_type" "sll0,load,load,load")
++   ldx.w\t%0,%1
++   movfr2gr.s\t%0,%1"
++  [(set_attr "move_type" "sll0,load,load,load,mftg")
+    (set_attr "mode" "DI")])
+ 
+ (define_insn "extend<SHORT:mode><GPR:mode>2"
+@@ -4110,14 +4111,52 @@
+   "movgr2fcsr\t$r%0,%1")
+ 
+ (define_insn "fclass_<fmt>"
+-  [(set (match_operand:ANYF 0 "register_operand" "=f")
+-	(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
+-		      UNSPEC_FCLASS))]
++  [(set (match_operand:SI 0 "register_operand" "=f")
++	(unspec:SI [(match_operand:ANYF 1 "register_operand" "f")]
++		   UNSPEC_FCLASS))]
+   "TARGET_HARD_FLOAT"
+   "fclass.<fmt>\t%0,%1"
+   [(set_attr "type" "unknown")
+    (set_attr "mode" "<MODE>")])
+ 
++(define_int_iterator FCLASS_MASK [68 136 952])
++(define_int_attr fclass_optab
++  [(68	"isinf")
++   (136	"isnormal")
++   (952	"isfinite")])
++
++(define_expand "<FCLASS_MASK:fclass_optab><ANYF:mode>2"
++  [(match_operand:SI   0 "register_operand" "=r")
++   (match_operand:ANYF 1 "register_operand" " f")
++   (const_int FCLASS_MASK)]
++  "TARGET_HARD_FLOAT"
++  {
++    rtx ft0 = gen_reg_rtx (SImode);
++    rtx t0 = gen_reg_rtx (word_mode);
++    rtx mask = GEN_INT (<FCLASS_MASK>);
++
++    emit_insn (gen_fclass_<ANYF:fmt> (ft0, operands[1]));
++
++    if (TARGET_64BIT)
++      emit_insn (gen_extend_insn (t0, ft0, DImode, SImode, 0));
++    else
++      emit_move_insn (t0, ft0);
++
++    emit_move_insn (t0, gen_rtx_AND (word_mode, t0, mask));
++    emit_move_insn (t0, gen_rtx_NE (word_mode, t0, const0_rtx));
++
++    if (TARGET_64BIT)
++      {
++	t0 = lowpart_subreg (SImode, t0, DImode);
++	SUBREG_PROMOTED_VAR_P (t0) = 1;
++	SUBREG_PROMOTED_SET (t0, SRP_SIGNED);
++      }
++
++    emit_move_insn (operands[0], t0);
++
++    DONE;
++  })
++
+ (define_insn "bytepick_w_<bytepick_imm>"
+   [(set (match_operand:SI 0 "register_operand" "=r")
+ 	(ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+diff --git a/gcc/testsuite/gcc.target/loongarch/fclass-compile.c b/gcc/testsuite/gcc.target/loongarch/fclass-compile.c
+new file mode 100644
+index 000000000..9c24d6e26
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/loongarch/fclass-compile.c
+@@ -0,0 +1,20 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=loongarch64 -mfpu=64 -mabi=lp64d" } */
++/* { dg-final { scan-assembler-times "fclass\\.s" 1 } } */
++/* { dg-final { scan-assembler-times "fclass\\.d" 1 } } */
++
++__attribute__ ((noipa)) int
++test_fclass_f (float f)
++{
++  return __builtin_isinf (f)
++	 | __builtin_isnormal (f) << 1
++	 | __builtin_isfinite (f) << 2;
++}
++
++__attribute__ ((noipa)) int
++test_fclass_d (double d)
++{
++  return __builtin_isinf (d)
++	 | __builtin_isnormal (d) << 1
++	 | __builtin_isfinite (d) << 2;
++}
+diff --git a/gcc/testsuite/gcc.target/loongarch/fclass-run.c b/gcc/testsuite/gcc.target/loongarch/fclass-run.c
+new file mode 100644
+index 000000000..e5585f9d5
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/loongarch/fclass-run.c
+@@ -0,0 +1,53 @@
++/* { dg-do run } */
++/* { dg-options "-O2 -fsignaling-nans -D_GNU_SOURCE -std=c23" } */
++/* { dg-require-effective-target fenv_exceptions } */
++
++#include <fenv.h>
++#include "fclass-compile.c"
++
++#define ASSERT_EQ(x, y) (void)(x == y || (__builtin_abort (), 1))
++
++int
++main (void)
++{
++  volatile float f_inf = __builtin_inff ();
++  volatile float f_zero = 0;
++  volatile float f_normal = 114.514;
++  volatile float f_subnormal = 1e-40;
++  volatile float f_qnan = __builtin_nanf ("");
++  volatile float f_snan = __builtin_nansf ("");
++  volatile double d_inf = __builtin_inf ();
++  volatile double d_zero = 0;
++  volatile double d_normal = 1919.810;
++  volatile double d_subnormal = 1e-320;
++  volatile double d_qnan = __builtin_nan ("");
++  volatile double d_snan = __builtin_nans ("");
++
++#if __loongarch_frlen >= 64
++  /* With fclass.{s/d} we shouldn't signal, even if the input is sNaN.
++     PR 66462.  */
++  feenableexcept (FE_INVALID);
++#endif
++
++  ASSERT_EQ (test_fclass_f (f_inf), 0b001);
++  ASSERT_EQ (test_fclass_f (-f_inf), 0b001);
++  ASSERT_EQ (test_fclass_f (f_zero), 0b100);
++  ASSERT_EQ (test_fclass_f (-f_zero), 0b100);
++  ASSERT_EQ (test_fclass_f (f_normal), 0b110);
++  ASSERT_EQ (test_fclass_f (-f_normal), 0b110);
++  ASSERT_EQ (test_fclass_f (f_subnormal), 0b100);
++  ASSERT_EQ (test_fclass_f (-f_subnormal), 0b100);
++  ASSERT_EQ (test_fclass_f (f_qnan), 0);
++  ASSERT_EQ (test_fclass_f (f_snan), 0);
++
++  ASSERT_EQ (test_fclass_d (d_inf), 0b001);
++  ASSERT_EQ (test_fclass_d (-d_inf), 0b001);
++  ASSERT_EQ (test_fclass_d (d_zero), 0b100);
++  ASSERT_EQ (test_fclass_d (-d_zero), 0b100);
++  ASSERT_EQ (test_fclass_d (d_normal), 0b110);
++  ASSERT_EQ (test_fclass_d (-d_normal), 0b110);
++  ASSERT_EQ (test_fclass_d (d_subnormal), 0b100);
++  ASSERT_EQ (test_fclass_d (-d_subnormal), 0b100);
++  ASSERT_EQ (test_fclass_d (d_qnan), 0);
++  ASSERT_EQ (test_fclass_d (d_snan), 0);
++}
+-- 
+2.43.0
+

0019-LoongArch-Add-support-to-annotate-tablejump.patch

@@ -0,0 +1,123 @@
+From f0416e6a2af1fb1f2b18a4410e679f25c57c5e9f Mon Sep 17 00:00:00 2001
+From: Xi Ruoyao <xry111@xry111.site>
+Date: Thu, 11 Jul 2024 19:43:48 +0800
+Subject: [PATCH 19/20] LoongArch: Add support to annotate tablejump
+
+This is per the request from the kernel developers.  For generating the
+ORC unwind info, the objtool program needs to analysis the control flow
+of a .o file.  If a jump table is used, objtool has to correlate the
+jump instruction with the table.
+
+On x86 (where objtool was initially developed) it's simple: a relocation
+entry natrually correlates them because one single instruction is used
+for table-based jump.  But on an RISC machine objtool would have to
+reconstruct the data flow if it must find out the correlation on its
+own.
+
+So, emit an additional section to store the correlation info as pairs of
+addresses, each pair contains the address of a jump instruction (jr) and
+the address of the jump table.  This is very trivial to implement in
+GCC.
+
+gcc/ChangeLog:
+
+	* config/loongarch/genopts/loongarch.opt.in
+	(mannotate-tablejump): New option.
+	* config/loongarch/loongarch.opt: Regenerate.
+	* config/loongarch/loongarch.md (tablejump<mode>): Emit
+	additional correlation info between the jump instruction and the
+	jump table, if -mannotate-tablejump.
+	* doc/invoke.texi: Document -mannotate-tablejump.
+
+gcc/testsuite/ChangeLog:
+
+	* gcc.target/loongarch/jump-table-annotate.c: New test.
+
+Suggested-by: Tiezhu Yang <yangtiezhu@loongson.cn>
+---
+ gcc/config/loongarch/genopts/loongarch.opt.in     |  4 ++++
+ gcc/config/loongarch/loongarch.md                 | 12 +++++++++++-
+ gcc/config/loongarch/loongarch.opt                |  4 ++++
+ .../gcc.target/loongarch/jump-table-annotate.c    | 15 +++++++++++++++
+ 4 files changed, 34 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/loongarch/jump-table-annotate.c
+
+diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
+index d00950cb4..d5bbf01d8 100644
+--- a/gcc/config/loongarch/genopts/loongarch.opt.in
++++ b/gcc/config/loongarch/genopts/loongarch.opt.in
+@@ -301,3 +301,7 @@ default value is 4.
+ ; CPUCFG independently, so we use bit flags to specify them.
+ TargetVariable
+ HOST_WIDE_INT la_isa_evolution = 0
++
++mannotate-tablejump
++Target Mask(ANNOTATE_TABLEJUMP) Save
++Annotate table jump instruction (jr {reg}) to correlate it with the jump table.
+diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
+index f70ca85bf..bd0825002 100644
+--- a/gcc/config/loongarch/loongarch.md
++++ b/gcc/config/loongarch/loongarch.md
+@@ -3496,12 +3496,22 @@
+   DONE;
+ })
+ 
++(define_mode_attr mode_size [(DI "8") (SI "4")])
++
+ (define_insn "@tablejump<mode>"
+   [(set (pc)
+ 	(match_operand:P 0 "register_operand" "e"))
+    (use (label_ref (match_operand 1 "" "")))]
+   ""
+-  "jr\t%0"
++  {
++    return TARGET_ANNOTATE_TABLEJUMP
++      ? "1:jr\t%0\n\t"
++	".pushsection\t.discard.tablejump_annotate\n\t"
++	"\t.<mode_size>byte\t1b\n\t"
++	"\t.<mode_size>byte\t%1\n\t"
++	".popsection"
++      : "jr\t%0";
++  }
+   [(set_attr "type" "jump")
+    (set_attr "mode" "none")])
+ 
+diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
+index 91cb5236a..6a396b539 100644
+--- a/gcc/config/loongarch/loongarch.opt
++++ b/gcc/config/loongarch/loongarch.opt
+@@ -310,6 +310,10 @@ default value is 4.
+ TargetVariable
+ HOST_WIDE_INT la_isa_evolution = 0
+ 
++mannotate-tablejump
++Target Mask(ANNOTATE_TABLEJUMP) Save
++Annotate table jump instruction (jr {reg}) to correlate it with the jump table
++
+ mfrecipe
+ Target Mask(ISA_FRECIPE) Var(la_isa_evolution)
+ Support frecipe.{s/d} and frsqrte.{s/d} instructions.
+diff --git a/gcc/testsuite/gcc.target/loongarch/jump-table-annotate.c b/gcc/testsuite/gcc.target/loongarch/jump-table-annotate.c
+new file mode 100644
+index 000000000..9d58e60e3
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/loongarch/jump-table-annotate.c
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++/* { dg-additional-options "-mannotate-tablejump" } */
++
++extern void asdf(int);
++void foo(int x) {
++  switch (x) {
++  case 0: asdf(10); break;
++  case 1: asdf(11); break;
++  case 2: asdf(12); break;
++  case 3: asdf(13); break;
++  case 4: asdf(14); break;
++  }
++}
++
++/* { dg-final { scan-assembler "\\.discard\\.tablejump_annotate" } } */
+-- 
+2.43.0
+

0020-LoongArch-Fix-up-r15-4130.patch

@@ -0,0 +1,32 @@
+From ff6fe2101c559b80e6f7c6f4e92a8732f20a28f0 Mon Sep 17 00:00:00 2001
+From: Xi Ruoyao <xry111@xry111.site>
+Date: Wed, 10 Jul 2024 12:15:23 +0800
+Subject: [PATCH 20/20] LoongArch: Fix up r15-4130
+
+An earlier version of the patch (lacking the regeneration of some files)
+was pushed.  Fix it up now.
+
+gcc/ChangeLog:
+
+	* config/loongarch/loongarch.opt: Regenerate.
+	* config/loongarch/loongarch.opt.urls: Regenerate.
+---
+ gcc/config/loongarch/loongarch.opt | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
+index 6a396b539..fae575452 100644
+--- a/gcc/config/loongarch/loongarch.opt
++++ b/gcc/config/loongarch/loongarch.opt
+@@ -312,7 +312,7 @@ HOST_WIDE_INT la_isa_evolution = 0
+ 
+ mannotate-tablejump
+ Target Mask(ANNOTATE_TABLEJUMP) Save
+-Annotate table jump instruction (jr {reg}) to correlate it with the jump table
++Annotate table jump instruction (jr {reg}) to correlate it with the jump table.
+ 
+ mfrecipe
+ Target Mask(ISA_FRECIPE) Var(la_isa_evolution)
+-- 
+2.43.0
+

0021-LoongArch-Change-OSDIR-for-distribution.patch

@@ -0,0 +1,25 @@
+From 25423cf92026221b7c8798533c40d3e6269a1d7c Mon Sep 17 00:00:00 2001
+From: Peng Fan <fanpeng@loongson.cn>
+Date: Thu, 31 Oct 2024 02:01:49 +0000
+Subject: [PATCH] LoongArch: Change OSDIR for distribution
+
+Signed-off-by: Peng Fan <fanpeng@loongson.cn>
+---
+ gcc/config/loongarch/t-linux | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/gcc/config/loongarch/t-linux b/gcc/config/loongarch/t-linux
+index 7cd7cde25..1d1f42596 100644
+--- a/gcc/config/loongarch/t-linux
++++ b/gcc/config/loongarch/t-linux
+@@ -28,4 +28,7 @@ ifeq ($(filter LA_DISABLE_MULTILIB,$(tm_defines)),)
+     MULTILIB_OSDIRNAMES += mabi.lp64f=$(MULTIOSDIR_lp64f)
+     MULTILIB_OSDIRNAMES += mabi.lp64s=$(MULTIOSDIR_lp64s)
+ 
++else
++    MULTILIB_OSDIRNAMES := ../lib64
++    MULTILIB_OPTIONS = mabi=lp64d
+ endif
+-- 
+2.45.2
+

0022-LoongArch-support-nonshared-extfloat.diff

@@ -0,0 +1,18 @@
+diff --git a/libstdc++-v3/src/nonshared98/extfloat.S b/libstdc++-v3/src/nonshared98/extfloat.S
+index b6e4164b5..bedada6d8 100644
+--- a/libstdc++-v3/src/nonshared98/extfloat.S
++++ b/libstdc++-v3/src/nonshared98/extfloat.S
+@@ -56,8 +56,12 @@
+ #elif defined __riscv && __riscv_xlen == 64
+ #define ALIGN1	.align 3
+ #define ALIGN3	.align 3
++#elif defined __loongarch64
++#define ALIGN1	.align 3
++#define ALIGN3	.align 3
+ #endif
+-#if defined __x86_64__ || defined __powerpc64__ || defined __s390x__ || defined __ia64__ || defined __aarch64__ || (defined __riscv && __riscv_xlen == 64)
++#if defined __x86_64__ || defined __powerpc64__ || defined __s390x__ || defined __ia64__ || defined __aarch64__ || (defined __riscv && __riscv_xlen == 64) \
++    || defined __loongarch64
+ #define SIZE1	32
+ #define SIZE2	16
+ #define OFF	16

0023-LoongArch-libstdcxx-nonshared.diff

@@ -0,0 +1,205 @@
+diff --git a/libstdc++-v3/src/nonshared17/cow-fs_dir.cc b/libstdc++-v3/src/nonshared17/cow-fs_dir.cc
+index 9525952b0..3a1c52edc 100644
+--- a/libstdc++-v3/src/nonshared17/cow-fs_dir.cc
++++ b/libstdc++-v3/src/nonshared17/cow-fs_dir.cc
+@@ -110,4 +110,6 @@ asm (".hidden _ZNKSt10filesystem28recursive_directory_iterator10_Dir_stack12curr
+ //asm (".hidden _ZNSt10filesystem4pathC1ISsS0_EERKT_NS0_6formatE");
+ asm (".hidden _ZNSt10filesystem28recursive_directory_iterator7__eraseEPSt10error_code");
+ //asm (".hidden _ZNKSt10filesystem4_Dir16dir_and_pathnameEv");
++#ifndef __loongarch64
+ asm (".hidden _ZNKSt10filesystem4_Dir7currentEv");
++#endif
+diff --git a/libstdc++-v3/src/nonshared17/cow-fs_ops.cc b/libstdc++-v3/src/nonshared17/cow-fs_ops.cc
+index 100565f43..0f9bec9be 100644
+--- a/libstdc++-v3/src/nonshared17/cow-fs_ops.cc
++++ b/libstdc++-v3/src/nonshared17/cow-fs_ops.cc
+@@ -88,4 +88,6 @@ asm (".hidden _ZNKSt10filesystem4path8filenameEv");
+ //asm (".hidden _ZSt16__do_uninit_copyINSt10filesystem4path8iteratorESt15_Deque_iteratorIS1_RS1_PS1_EET0_T_S8_S7_");
+ //asm (".hidden _ZSt4copyINSt10filesystem4path8iteratorESt15_Deque_iteratorIS1_RS1_PS1_EET0_T_S8_S7_");
+ #endif
++#ifndef __loongarch64
+ asm (".hidden _ZNSs4swapERSs");
++#endif
+diff --git a/libstdc++-v3/src/nonshared17/cow-fs_path.cc b/libstdc++-v3/src/nonshared17/cow-fs_path.cc
+index 630646d8e..954a09d3e 100644
+--- a/libstdc++-v3/src/nonshared17/cow-fs_path.cc
++++ b/libstdc++-v3/src/nonshared17/cow-fs_path.cc
+@@ -93,28 +93,36 @@ asm (".hidden _ZNKSt10filesystem4path5_List5_Impl4copyEv");
+ #ifndef __riscv
+ asm (".hidden _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv");
+ #endif
++#ifndef __loongarch64
+ asm (".hidden _ZNSbIwSt11char_traitsIwESaIwEE6resizeEmw");
+ asm (".hidden _ZNSbIwSt11char_traitsIwESaIwEE7reserveEm");
+ asm (".hidden _ZNSbIwSt11char_traitsIwESaIwEE9_M_mutateEmmm");
+ asm (".hidden _ZNSs6insertEmPKcm");
+ asm (".hidden _ZNSs6resizeEmc");
+-asm (".hidden _ZNSs7reserveEm");
+ asm (".hidden _ZNSs9_M_mutateEmmm");
+ asm (".hidden _ZNSsC1ERKSsmm");
+-#ifndef __riscv
++asm (".hidden _ZNSs7reserveEm");
++#endif
++#if !defined __riscv && !defined __loongarch64
+ asm (".hidden _ZNSsC2ERKSsmm");
+ asm (".hidden _ZNSt10filesystem4pathD2Ev");
+ #endif
++#ifndef __loongarch64
+ asm (".hidden _ZSt16__do_str_codecvtISbIwSt11char_traitsIwESaIwEEcSt7codecvtIwc11__mbstate_tES5_MS6_KFNSt12codecvt_base6resultERS5_PKcSB_RSB_PwSD_RSD_EEbPKT0_SJ_RT_RKT1_RT2_RmT3_");
++#endif
+ //asm (".hidden _ZSt16__do_str_codecvtISswSt7codecvtIwc11__mbstate_tES1_MS2_KFNSt12codecvt_base6resultERS1_PKwS7_RS7_PcS9_RS9_EEbPKT0_SF_RT_RKT1_RT2_RmT3_");
+ #endif
++#ifndef __loongarch64
+ asm (".hidden _ZNSbIwSt11char_traitsIwESaIwEE12_M_leak_hardEv");
+ asm (".hidden _ZNSt10filesystem4path5_List5beginEv");
+-#ifndef __s390x__
++#endif
++#if !defined(__s390x__) && !defined(__loongarch64)
+ asm (".hidden _ZNSt10filesystem4path7_Parser4nextEv");
+ #endif
++#ifndef __loongarch64
+ asm (".hidden _ZNSt10filesystem4pathD1Ev");
+ asm (".hidden _ZNSs12_M_leak_hardEv");
++#endif
+ #ifdef __i386__
+ asm (".hidden _ZNSbIwSt11char_traitsIwESaIwEE6resizeEjw");
+ asm (".hidden _ZNSbIwSt11char_traitsIwESaIwEE7reserveEj");
+diff --git a/libstdc++-v3/src/nonshared17/floating_from_chars.cc b/libstdc++-v3/src/nonshared17/floating_from_chars.cc
+index 4ef0871a4..0895e120a 100644
+--- a/libstdc++-v3/src/nonshared17/floating_from_chars.cc
++++ b/libstdc++-v3/src/nonshared17/floating_from_chars.cc
+@@ -25,9 +25,11 @@
+ //asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcENSt3pmr21polymorphic_allocatorIcEEE9_M_createERjj");
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcENSt3pmr21polymorphic_allocatorIcEEE9_M_mutateEjjPKcj");
+ #else
++#ifndef __loongarch64
+ //asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcENSt3pmr21polymorphic_allocatorIcEEE9_M_createERmm");
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcENSt3pmr21polymorphic_allocatorIcEEE9_M_mutateEmmPKcm");
+ #endif
++#endif
+ #if defined(__s390x__) || defined(__powerpc64__)
+ //asm (".hidden _ZSt10from_charsPKcS0_RgSt12chars_format");
+ #endif
+@@ -43,8 +45,10 @@ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcENSt3pmr21polymorphi
+ #if defined(__i386__) || (defined(__powerpc__) && !defined(__powerpc64__))
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcENSt3pmr21polymorphic_allocatorIcEEE15_M_replace_coldEPcjPKcjj");
+ #else
++#ifndef __loongarch64
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcENSt3pmr21polymorphic_allocatorIcEEE15_M_replace_coldEPcmPKcmm");
+ #endif
++#endif
+ #ifndef __riscv
+ asm (".hidden _ZNSt8__detail31__from_chars_alnum_to_val_tableILb0EE5valueE");
+ #endif
+diff --git a/libstdc++-v3/src/nonshared17/floating_from_chars110.cc b/libstdc++-v3/src/nonshared17/floating_from_chars110.cc
+index 3c7cd9610..7a46c19fd 100644
+--- a/libstdc++-v3/src/nonshared17/floating_from_chars110.cc
++++ b/libstdc++-v3/src/nonshared17/floating_from_chars110.cc
+@@ -29,9 +29,11 @@
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcENSt3pmr21polymorphic_allocatorIcEEE15_M_replace_coldEPcjPKcjj");
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcENSt3pmr21polymorphic_allocatorIcEEE9_M_mutateEjjPKcj");
+ #else
++#ifndef __loongarch64
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcENSt3pmr21polymorphic_allocatorIcEEE15_M_replace_coldEPcmPKcmm");
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcENSt3pmr21polymorphic_allocatorIcEEE9_M_mutateEmmPKcm");
+ #endif
++#endif
+ #ifndef __riscv
+ asm (".hidden _ZNSt8__detail31__from_chars_alnum_to_val_tableILb0EE5valueE");
+ #endif
+diff --git a/libstdc++-v3/src/nonshared17/floating_to_chars110.cc b/libstdc++-v3/src/nonshared17/floating_to_chars110.cc
+index de9465513..b2ef2edce 100644
+--- a/libstdc++-v3/src/nonshared17/floating_to_chars110.cc
++++ b/libstdc++-v3/src/nonshared17/floating_to_chars110.cc
+@@ -24,7 +24,7 @@
+ #include "../c++17/floating_to_chars.cc"
+ //asm (".hidden _ZSt12__to_chars_iIoENSt9enable_ifIXsrSt5__or_IJS1_IJSt7is_sameINSt9remove_cvIT_E4typeEaES2_IS6_sES2_IS6_iES2_IS6_lES2_IS6_xES2_IS6_nEEES1_IJS2_IS6_hES2_IS6_tES2_IS6_jES2_IS6_mES2_IS6_yES2_IS6_oEEES2_IcS6_EEE5valueESt15to_chars_resultE4typeEPcSQ_S4_i");
+ //asm (".hidden _ZSt12__to_chars_iIoENSt9enable_ifIXsrSt5__or_IIS1_IISt7is_sameINSt9remove_cvIT_E4typeEaES2_IS6_sES2_IS6_iES2_IS6_lES2_IS6_xES2_IS6_nEEES1_IIS2_IS6_hES2_IS6_tES2_IS6_jES2_IS6_mES2_IS6_yES2_IS6_oEEES2_IcS6_EEE5valueESt15to_chars_resultE4typeEPcSQ_S4_i");
+-#ifndef __riscv
++#if !defined(__riscv) && !defined(__loongarch64)
+ asm (".hidden _ZNSt8__detail18__to_chars_10_implIjEEvPcjT_");
+ #endif
+ #if !defined(__i386__)
+diff --git a/libstdc++-v3/src/nonshared17/fs_dir.cc b/libstdc++-v3/src/nonshared17/fs_dir.cc
+index 655b04794..12d96ae35 100644
+--- a/libstdc++-v3/src/nonshared17/fs_dir.cc
++++ b/libstdc++-v3/src/nonshared17/fs_dir.cc
+@@ -43,8 +43,10 @@ asm (".hidden _ZNSt10filesystem9_Dir_base7advanceEbRSt10error_code");
+ //asm (".hidden _ZNSt10filesystem9_Dir_baseC1EPKcbRSt10error_code");
+ //asm (".hidden _ZNSt10filesystem9_Dir_baseC2EPKcbRSt10error_code");
+ #endif
++#ifndef __loongarch64
+ asm (".hidden _ZNSt10filesystem7__cxx114pathC1INSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES1_EERKT_NS1_6formatE");
+-#ifndef __riscv
++#endif
++#if !defined(__riscv) && !defined(__loongarch64)
+ asm (".hidden _ZNSt10filesystem7__cxx114pathC2INSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES1_EERKT_NS1_6formatE");
+ asm (".hidden _ZNSt12__shared_ptrINSt10filesystem7__cxx1128recursive_directory_iterator10_Dir_stackELN9__gnu_cxx12_Lock_policyE2EE4swapERS6_");
+ asm (".hidden _ZNSt12__shared_ptrINSt10filesystem7__cxx1128recursive_directory_iterator10_Dir_stackELN9__gnu_cxx12_Lock_policyE2EE5resetEv");
+@@ -99,7 +101,7 @@ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt10filesystem7__cxx1128recursive_
+ asm (".hidden _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag");
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt10filesystem7__cxx114_DirESaIS2_ELN9__gnu_cxx12_Lock_policyE2EED2Ev");
+ #endif
+-#if !defined__i386__ && !defined __riscv
++#if !defined__i386__ && !defined __riscv && !defined __loongarch64
+ asm (".hidden _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv");
+ //asm (".hidden _ZNSt5dequeINSt10filesystem7__cxx114_DirESaIS2_EE17_M_reallocate_mapEmb");
+ #endif
+@@ -114,6 +116,8 @@ asm (".hidden _ZNSt10filesystem9_Dir_base7advanceEbRSt10error_code");
+ asm (".hidden _ZNKSt10filesystem7__cxx1128recursive_directory_iterator10_Dir_stack12current_pathEv");
+ asm (".hidden _ZNSt10filesystem7__cxx1128recursive_directory_iterator7__eraseEPSt10error_code");
+ //asm (".hidden _ZNKSt10filesystem7__cxx114_Dir16dir_and_pathnameEv");
++#ifndef __loongarch64
+ asm (".hidden _ZNKSt10filesystem7__cxx114_Dir7currentEv");
++#endif
+ //asm (".hidden _ZNSt10filesystem7__cxx114_DirC1ERKNS0_4pathEbbbRSt10error_code");
+ //asm (".hidden _ZNSt10filesystem7__cxx114_DirC2ERKNS0_4pathEbbbRSt10error_code");
+diff --git a/libstdc++-v3/src/nonshared17/fs_path80.cc b/libstdc++-v3/src/nonshared17/fs_path80.cc
+index 16576bbd3..b5e9f1a79 100644
+--- a/libstdc++-v3/src/nonshared17/fs_path80.cc
++++ b/libstdc++-v3/src/nonshared17/fs_path80.cc
+@@ -128,12 +128,16 @@ asm (".hidden _ZNSt12system_errorC1ESt10error_codeRKNSt7__cxx1112basic_stringIcS
+ asm (".hidden _ZNSt12system_errorC2ESt10error_codeRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE");
+ #endif
+ //asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_assignERKS4_");
++#ifndef __loongarch64
+ asm (".hidden _ZNSt10filesystem7__cxx114path5_List5beginEv");
++#endif
+ #ifndef __i386__
+ //asm (".hidden _ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6resizeEmw");
+ //asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm");
+ //asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm");
++#ifndef __loongarch64
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6resizeEmc");
++#endif
+ //asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm");
+ //asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm");
+ #ifndef __riscv
+diff --git a/libstdc++-v3/src/nonshared17/memory_resource.cc b/libstdc++-v3/src/nonshared17/memory_resource.cc
+index 36bfac568..cb1eb14de 100644
+--- a/libstdc++-v3/src/nonshared17/memory_resource.cc
++++ b/libstdc++-v3/src/nonshared17/memory_resource.cc
+@@ -73,7 +73,9 @@ asm (".hidden _ZNSt3pmr28unsynchronized_pool_resource12_M_find_poolEj");
+ #ifdef __powerpc64__
+ //asm (".hidden _ZNSt3pmr15__pool_resource5_Pool10deallocateEPNS_15memory_resourceEPv");
+ #endif
++#ifndef __loongarch64
+ asm (".hidden _ZNSt22__shared_mutex_pthread6unlockEv");
++#endif
+ #if defined(__i386__) || (defined(__powerpc__) && !defined(__powerpc64__))
+ asm (".hidden _ZNSt6vectorINSt3pmr15__pool_resource9_BigBlockENS0_21polymorphic_allocatorIS2_EEE17_M_realloc_appendIIRjS7_EEEvDpOT_");
+ asm (".hidden _ZNSt6vectorINSt3pmr15__pool_resource9_BigBlockENS0_21polymorphic_allocatorIS2_EEE17_M_realloc_appendIJRjS7_EEEvDpOT_");
+diff --git a/libstdc++-v3/src/nonshared20/tzdb80.cc b/libstdc++-v3/src/nonshared20/tzdb80.cc
+index 1e88dba3b..1a3f769ac 100644
+--- a/libstdc++-v3/src/nonshared20/tzdb80.cc
++++ b/libstdc++-v3/src/nonshared20/tzdb80.cc
+@@ -149,7 +149,9 @@ asm (".hidden _ZTSSt19_Sp_make_shared_tag");
+ asm (".hidden _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv");
+ #endif
+ #endif
++#ifndef __loongarch64
+ asm (".hidden _ZSt23__atomic_wait_address_vIiZNKSt13__atomic_baseIiE4waitEiSt12memory_orderEUlvE_EvPKT_S4_T0_");
++#endif
+ #ifndef __riscv
+ asm (".hidden _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv");
+ asm (".hidden _ZNSt10unique_ptrINSt10filesystem7__cxx114path5_List5_ImplENS3_13_Impl_deleterEED2Ev");

GCC14-1004-riscv-lib64.patch

@@ -0,0 +1,66 @@
+From 8c8e61a37b253317a55031527a351f433a4192f7 Mon Sep 17 00:00:00 2001
+From: YunQiang Su <yunqiang@isrc.iscas.ac.cn>
+Date: Mon, 14 Oct 2024 10:09:46 +0800
+Subject: [PATCH 3/3] RISC-V: Install libstdc++/libcc1 etc to /lib64 instead of
+ lib
+
+The problem is that if we are configured with `--disable-multilib`,
+  gcc -print-multi-os-directory
+outputs
+  .
+Thus the dest to install libraries is set to
+  /usr/lib/.
+While other platforms (x86-64, arm64) it will be
+  /usr/lib/../lib64
+Let's sync riscv64 with them
+
+Another problem is that
+  gcc -print-file-name=libzstd.so.1
+will output
+  /usr/lib64/lp64d/../lib64/libzstd.so.1
+which is also need to patched.
+---
+ gcc/config.gcc               | 3 +++
+ gcc/config/riscv/linux.h     | 2 ++
+ gcc/config/riscv/t-openEuler | 2 ++
+ 3 files changed, 7 insertions(+)
+ create mode 100644 gcc/config/riscv/t-openEuler
+
+diff --git a/gcc/config.gcc b/gcc/config.gcc
+index 95c91ee02..531e7fa45 100644
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
+@@ -2490,6 +2490,9 @@ riscv*-*-linux*)
+ 	xyes) tmake_file="${tmake_file} riscv/t-linux-multilib" ;;
+ 	*) echo "Unknown value for enable_multilib"; exit 1
+ 	esac
++	case "x${target_vendor}" in
++	xopenEuler) tmake_file="${tmake_file} riscv/t-openEuler"
++	esac
+ 	tmake_file="${tmake_file} riscv/t-riscv riscv/t-linux"
+ 	tm_defines="${tm_defines} TARGET_DEFAULT_ASYNC_UNWIND_TABLES=1"
+ 	gnu_ld=yes
+diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
+index 3c3562271..2acbdc688 100644
+--- a/gcc/config/riscv/linux.h
++++ b/gcc/config/riscv/linux.h
+@@ -62,6 +62,8 @@ along with GCC; see the file COPYING3.  If not see
+     %{static:-static} %{static-pie:-static -pie --no-dynamic-linker -z text}}"
+ 
+ #define STARTFILE_PREFIX_SPEC 			\
++   "/lib" XLEN_SPEC "/ " 			\
++   "/usr/lib" XLEN_SPEC "/ " 			\
+    "/lib" XLEN_SPEC "/" ABI_SPEC "/ "		\
+    "/usr/lib" XLEN_SPEC "/" ABI_SPEC "/ "	\
+    "/lib/ "					\
+diff --git a/gcc/config/riscv/t-openEuler b/gcc/config/riscv/t-openEuler
+new file mode 100644
+index 000000000..26541dd08
+--- /dev/null
++++ b/gcc/config/riscv/t-openEuler
+@@ -0,0 +1,2 @@
++MULTILIB_OPTIONS = mabi=lp64d
++MULTILIB_DIRNAMES = ../lib64
+-- 
+2.43.0
+

GCC14-1005-libstdc-compat-Update-symbol-list-for-RISC-V-64.patch

@@ -0,0 +1,826 @@
+From aab55352512fe713b7eac5c41d2467e0601d02eb Mon Sep 17 00:00:00 2001
+From: Your Name <you@example.com>
+Date: Mon, 9 Dec 2024 15:16:01 +0800
+Subject: [PATCH 2/2] libstdc++-compat: Update symbol list for RISC-V 64
+
+---
+ libstdc++-v3/src/nonshared11/codecvt80.cc     |  2 +
+ .../src/nonshared11/cow-sstream-inst80.cc     |  4 ++
+ .../src/nonshared11/cxx11-ios_failure80.cc    | 12 ++++++
+ .../src/nonshared11/sstream-inst80.cc         |  4 ++
+ libstdc++-v3/src/nonshared17/cow-fs_dir.cc    | 12 +++++-
+ libstdc++-v3/src/nonshared17/cow-fs_ops.cc    | 10 +++++
+ libstdc++-v3/src/nonshared17/cow-fs_path.cc   | 18 +++++++++
+ .../src/nonshared17/cow-string-inst110.cc     |  8 ++++
+ .../src/nonshared17/floating_from_chars.cc    |  2 +
+ .../src/nonshared17/floating_from_chars110.cc |  2 +
+ .../src/nonshared17/floating_to_chars110.cc   |  2 +
+ libstdc++-v3/src/nonshared17/fs_dir.cc        | 16 +++++++-
+ libstdc++-v3/src/nonshared17/fs_ops80.cc      | 10 +++++
+ libstdc++-v3/src/nonshared17/fs_path80.cc     | 26 ++++++++++++
+ .../src/nonshared17/memory_resource.cc        | 10 +++++
+ .../src/nonshared17/string-inst110.cc         |  8 ++++
+ libstdc++-v3/src/nonshared20/tzdb110.cc       |  2 +
+ libstdc++-v3/src/nonshared20/tzdb80.cc        | 40 +++++++++++++++++++
+ libstdc++-v3/src/nonshared98/extfloat.S       |  5 ++-
+ 19 files changed, 190 insertions(+), 3 deletions(-)
+
+diff --git a/libstdc++-v3/src/nonshared11/codecvt80.cc b/libstdc++-v3/src/nonshared11/codecvt80.cc
+index c903548a8..fb42c0451 100644
+--- a/libstdc++-v3/src/nonshared11/codecvt80.cc
++++ b/libstdc++-v3/src/nonshared11/codecvt80.cc
+@@ -22,6 +22,7 @@
+ 
+ #define _GLIBCXX_NONSHARED_CXX11_80
+ #include "../c++11/codecvt.cc"
++#ifndef __riscv
+ asm (".hidden _ZTISt12codecvt_base");
+ asm (".hidden _ZTSSt12codecvt_base");
+ asm (".hidden _ZTISt23__codecvt_abstract_baseIDic11__mbstate_tE");
+@@ -36,3 +37,4 @@ asm (".hidden _ZTSSt23__codecvt_abstract_baseIDiDu11__mbstate_tE");
+ asm (".hidden _ZTSSt23__codecvt_abstract_baseIDsDu11__mbstate_tE");
+ asm (".hidden _ZTVSt23__codecvt_abstract_baseIDiDu11__mbstate_tE");
+ asm (".hidden _ZTVSt23__codecvt_abstract_baseIDsDu11__mbstate_tE");
++#endif
+diff --git a/libstdc++-v3/src/nonshared11/cow-sstream-inst80.cc b/libstdc++-v3/src/nonshared11/cow-sstream-inst80.cc
+index bc72608d3..889637988 100644
+--- a/libstdc++-v3/src/nonshared11/cow-sstream-inst80.cc
++++ b/libstdc++-v3/src/nonshared11/cow-sstream-inst80.cc
+@@ -47,7 +47,11 @@ _GLIBCXX_END_NAMESPACE_VERSION
+ 
+ asm (".hidden _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEED0Ev");
+ asm (".hidden _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt15basic_stringbufIcSt11char_traitsIcESaIcEED2Ev");
++#endif
+ asm (".hidden _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEED0Ev");
+ asm (".hidden _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt15basic_stringbufIwSt11char_traitsIwESaIwEED2Ev");
++#endif
+diff --git a/libstdc++-v3/src/nonshared11/cxx11-ios_failure80.cc b/libstdc++-v3/src/nonshared11/cxx11-ios_failure80.cc
+index 514cd21d4..c768a493d 100644
+--- a/libstdc++-v3/src/nonshared11/cxx11-ios_failure80.cc
++++ b/libstdc++-v3/src/nonshared11/cxx11-ios_failure80.cc
+@@ -24,9 +24,12 @@
+ asm (".hidden _ZNKSt19__iosfail_type_info11__do_upcastEPKN10__cxxabiv117__class_type_infoEPPv");
+ asm (".hidden _ZNSt13__ios_failureD0Ev");
+ asm (".hidden _ZNSt13__ios_failureD1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt13__ios_failureD2Ev");
++#endif
+ asm (".hidden _ZNSt19__iosfail_type_infoD0Ev");
+ asm (".hidden _ZNSt19__iosfail_type_infoD1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt19__iosfail_type_infoD2Ev");
+ asm (".hidden _ZTISt13__ios_failure");
+ asm (".hidden _ZTISt19__iosfail_type_info");
+@@ -36,15 +39,24 @@ asm (".hidden _ZTVSt13__ios_failure");
+ asm (".hidden _ZTVSt19__iosfail_type_info");
+ asm (".hidden _ZNSt8ios_base7failureB5cxx11D2Ev");
+ asm (".hidden _ZTVNSt8ios_base7failureB5cxx11E");
++#endif
+ asm (".hidden _ZNSt8ios_base7failureB5cxx11D1Ev");
+ asm (".hidden _ZNSt8ios_base7failureB5cxx11D0Ev");
+ asm (".hidden _ZNKSt8ios_base7failureB5cxx114whatEv");
++#ifndef __riscv
+ asm (".hidden _ZNSt8ios_base7failureB5cxx11C2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE");
++#endif
+ asm (".hidden _ZNSt8ios_base7failureB5cxx11C1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE");
++#ifndef __riscv
+ asm (".hidden _ZNSt8ios_base7failureB5cxx11C2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKSt10error_code");
++#endif
+ asm (".hidden _ZNSt8ios_base7failureB5cxx11C1ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKSt10error_code");
++#ifndef __riscv
+ asm (".hidden _ZNSt8ios_base7failureB5cxx11C2EPKcRKSt10error_code");
++#endif
+ asm (".hidden _ZNSt8ios_base7failureB5cxx11C1EPKcRKSt10error_code");
++#ifndef __riscv
+ asm (".hidden _ZTSNSt8ios_base7failureB5cxx11E");
+ asm (".hidden _ZTINSt8ios_base7failureB5cxx11E");
++#endif
+ asm (".hidden _ZSt19__throw_ios_failurePKc");
+diff --git a/libstdc++-v3/src/nonshared11/sstream-inst80.cc b/libstdc++-v3/src/nonshared11/sstream-inst80.cc
+index 574f86d59..8082817f2 100644
+--- a/libstdc++-v3/src/nonshared11/sstream-inst80.cc
++++ b/libstdc++-v3/src/nonshared11/sstream-inst80.cc
+@@ -49,7 +49,11 @@ _GLIBCXX_END_NAMESPACE_VERSION
+ 
+ asm (".hidden _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED0Ev");
+ asm (".hidden _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED2Ev");
++#endif
+ asm (".hidden _ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEED0Ev");
+ asm (".hidden _ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt7__cxx1115basic_stringbufIwSt11char_traitsIwESaIwEED2Ev");
++#endif
+diff --git a/libstdc++-v3/src/nonshared17/cow-fs_dir.cc b/libstdc++-v3/src/nonshared17/cow-fs_dir.cc
+index 59538ebfa..9525952b0 100644
+--- a/libstdc++-v3/src/nonshared17/cow-fs_dir.cc
++++ b/libstdc++-v3/src/nonshared17/cow-fs_dir.cc
+@@ -21,18 +21,23 @@
+ // <http://www.gnu.org/licenses/>.
+ 
+ #include "../c++17/cow-fs_dir.cc"
++#ifndef __riscv
+ asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem28recursive_directory_iterator10_Dir_stackELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info");
+ asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem28recursive_directory_iterator10_Dir_stackELN9__gnu_cxx12_Lock_policyE2EE3getEv");
+ asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem28recursive_directory_iterator10_Dir_stackELN9__gnu_cxx12_Lock_policyE2EE6uniqueEv");
+ asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem28recursive_directory_iterator10_Dir_stackELN9__gnu_cxx12_Lock_policyE2EE9use_countEv");
++#endif
+ //asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem28recursive_directory_iterator10_Dir_stackELN9__gnu_cxx12_Lock_policyE2EEcvbEv");
++#ifndef __riscv
+ asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem4_DirELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info");
+ asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem4_DirELN9__gnu_cxx12_Lock_policyE2EE3getEv");
+ asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem4_DirELN9__gnu_cxx12_Lock_policyE2EE6uniqueEv");
+ asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem4_DirELN9__gnu_cxx12_Lock_policyE2EE9use_countEv");
++#endif
+ //asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem4_DirELN9__gnu_cxx12_Lock_policyE2EEcvbEv");
+ asm (".hidden _ZNSt10filesystem4_Dir7advanceEbRSt10error_code");
+ asm (".hidden _ZNSt10filesystem4_DirD1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt10filesystem4_DirD2Ev");
+ #ifdef __i386__
+ asm (".hidden _ZNSt10filesystem9_Dir_base7advanceEbRSt10error_code");
+@@ -61,11 +66,15 @@ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt10filesystem4_DirESaIS1_ELN9__gn
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt10filesystem4_DirESaIS1_ELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info");
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt10filesystem4_DirESaIS1_ELN9__gnu_cxx12_Lock_policyE2EED0Ev");
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt10filesystem4_DirESaIS1_ELN9__gnu_cxx12_Lock_policyE2EED1Ev");
++#endif
+ asm (".hidden _ZNSt5dequeINSt10filesystem4_DirESaIS1_EE12emplace_backIIS1_EEERS1_DpOT_");
++#ifndef __riscv
+ asm (".hidden _ZNSt5dequeINSt10filesystem4_DirESaIS1_EE12emplace_backIJS1_EEERS1_DpOT_");
++#endif
+ //asm (".hidden _ZNSt5dequeINSt10filesystem4_DirESaIS1_EE16_M_push_back_auxIIRP11__dirstreamRKNS0_4pathEEEEvDpOT_");
+ //asm (".hidden _ZNSt5dequeINSt10filesystem4_DirESaIS1_EE16_M_push_back_auxIJRP11__dirstreamRKNS0_4pathEEEEvDpOT_");
+ asm (".hidden _ZNSt5dequeINSt10filesystem4_DirESaIS1_EED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt5dequeINSt10filesystem4_DirESaIS1_EED2Ev");
+ asm (".hidden _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE");
+ asm (".hidden _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE");
+@@ -85,7 +94,8 @@ asm (".hidden _ZNSsC2ISaIcEEEPKcRKS0_");
+ #endif
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt10filesystem28recursive_directory_iterator10_Dir_stackESaIS2_ELN9__gnu_cxx12_Lock_policyE2EED2Ev");
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt10filesystem4_DirESaIS1_ELN9__gnu_cxx12_Lock_policyE2EED2Ev");
+-#ifndef __i386__
++#endif
++#if !defined(__i386__) && !defined(__riscv)
+ //asm (".hidden _ZNSt5dequeINSt10filesystem4_DirESaIS1_EE17_M_reallocate_mapEmb");
+ asm (".hidden _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv");
+ #endif
+diff --git a/libstdc++-v3/src/nonshared17/cow-fs_ops.cc b/libstdc++-v3/src/nonshared17/cow-fs_ops.cc
+index 775f18db5..100565f43 100644
+--- a/libstdc++-v3/src/nonshared17/cow-fs_ops.cc
++++ b/libstdc++-v3/src/nonshared17/cow-fs_ops.cc
+@@ -21,22 +21,30 @@
+ // <http://www.gnu.org/licenses/>.
+ 
+ #include "../c++17/cow-fs_ops.cc"
++#ifndef __riscv
+ asm (".hidden _ZNSt15_Sp_counted_ptrIDnLN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv");
+ asm (".hidden _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv");
+ asm (".hidden _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv");
++#endif
+ //asm (".hidden _ZNSt5dequeINSt10filesystem4pathESaIS1_EE16_M_push_back_auxIJRKS1_EEEvDpOT_");
+ //asm (".hidden _ZNSt5dequeINSt10filesystem4pathESaIS1_EE16_M_push_back_auxIIRKS1_EEEvDpOT_");
+ //asm (".hidden _ZNSt5dequeINSt10filesystem4pathESaIS1_EE12emplace_backIJS1_EEERS1_DpOT_");
+ //asm (".hidden _ZNSt5dequeINSt10filesystem4pathESaIS1_EE12emplace_backIIS1_EEERS1_DpOT_");
+ asm (".hidden _ZNSt5dequeINSt10filesystem4pathESaIS1_EED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt5dequeINSt10filesystem4pathESaIS1_EED2Ev");
++#endif
+ asm (".hidden _ZNSt10unique_ptrINSt10filesystem4path5_List5_ImplENS2_13_Impl_deleterEED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt10unique_ptrINSt10filesystem4path5_List5_ImplENS2_13_Impl_deleterEED2Ev");
++#endif
+ asm (".hidden _ZSt14__copy_move_a1ILb1EPNSt10filesystem4pathES1_EN9__gnu_cxx11__enable_ifIXsrSt23__is_random_access_iterIT0_NSt15iterator_traitsIS6_E17iterator_categoryEE7__valueESt15_Deque_iteratorIT1_RSC_PSC_EE6__typeES6_S6_SF_");
+ asm (".hidden _ZSt23__copy_move_backward_a1ILb1EPNSt10filesystem4pathES1_EN9__gnu_cxx11__enable_ifIXsrSt23__is_random_access_iterIT0_NSt15iterator_traitsIS6_E17iterator_categoryEE7__valueESt15_Deque_iteratorIT1_RSC_PSC_EE6__typeES6_S6_SF_");
+ //asm (".hidden _ZSt8_DestroyISt15_Deque_iteratorINSt10filesystem4pathERS2_PS2_EEvT_S6_");
+ asm (".hidden _ZNSsC1ISaIcEEEPKcRKS0_");
++#ifndef __riscv
+ asm (".hidden _ZNSsC2ISaIcEEEPKcRKS0_");
++#endif
+ #ifndef __i386__
+ //asm (".hidden _ZNSs9_M_mutateEmmm");
+ asm (".hidden _ZNSt11_Deque_baseINSt10filesystem4pathESaIS1_EE17_M_initialize_mapEm");
+@@ -47,8 +55,10 @@ asm (".hidden _ZNSt5dequeINSt10filesystem4pathESaIS1_EE24_M_new_elements_at_fron
+ //asm (".hidden _ZNSs6resizeEmc");
+ //asm (".hidden _ZNSt10filesystem4pathD1Ev");
+ //asm (".hidden _ZNSt10filesystem4pathD2Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv");
+ #endif
++#endif
+ #if defined(__x86_64__)
+ //asm (".hidden _ZSt13move_backwardISt15_Deque_iteratorINSt10filesystem4pathERS2_PS2_ES5_ET0_T_S7_S6_");
+ //asm (".hidden _ZSt4moveISt15_Deque_iteratorINSt10filesystem4pathERS2_PS2_ES5_ET0_T_S7_S6_");
+diff --git a/libstdc++-v3/src/nonshared17/cow-fs_path.cc b/libstdc++-v3/src/nonshared17/cow-fs_path.cc
+index b22ac70da..630646d8e 100644
+--- a/libstdc++-v3/src/nonshared17/cow-fs_path.cc
++++ b/libstdc++-v3/src/nonshared17/cow-fs_path.cc
+@@ -21,18 +21,23 @@
+ // <http://www.gnu.org/licenses/>.
+ 
+ #include "../c++17/cow-fs_path.cc"
++#ifndef __riscv
+ asm (".hidden _ZNKSt12__shared_ptrIKNSt10filesystem16filesystem_error5_ImplELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info");
+ asm (".hidden _ZNKSt12__shared_ptrIKNSt10filesystem16filesystem_error5_ImplELN9__gnu_cxx12_Lock_policyE2EE3getEv");
+ asm (".hidden _ZNKSt12__shared_ptrIKNSt10filesystem16filesystem_error5_ImplELN9__gnu_cxx12_Lock_policyE2EE6uniqueEv");
+ asm (".hidden _ZNKSt12__shared_ptrIKNSt10filesystem16filesystem_error5_ImplELN9__gnu_cxx12_Lock_policyE2EE9use_countEv");
+ asm (".hidden _ZNKSt12__shared_ptrIKNSt10filesystem16filesystem_error5_ImplELN9__gnu_cxx12_Lock_policyE2EEcvbEv");
++#endif
+ asm (".hidden _ZNKSt23__codecvt_abstract_baseIwc11__mbstate_tE2inERS0_PKcS4_RS4_PwS6_RS6_");
+ asm (".hidden _ZNKSt23__codecvt_abstract_baseIwc11__mbstate_tE3outERS0_PKwS4_RS4_PcS6_RS6_");
++#ifndef __riscv
+ asm (".hidden _ZNSt10filesystem4path19preferred_separatorE");
++#endif
+ asm (".hidden _ZNSt10filesystem4path5_List5clearEv");
+ asm (".hidden _ZNSt10filesystem4path5_List5_Impl13_M_erase_fromEPKNS0_5_CmptE");
+ asm (".hidden _ZNSt10filesystem4path5_List7reserveEib");
+ asm (".hidden _ZNSt10filesystem4path5_ListaSERKS1_");
++#ifndef __riscv
+ asm (".hidden _ZNSt10filesystem4path5_ListC2ERKS1_");
+ asm (".hidden _ZNSt10filesystem4path5_ListC2Ev");
+ asm (".hidden _ZNSt12__shared_ptrIKNSt10filesystem16filesystem_error5_ImplELN9__gnu_cxx12_Lock_policyE2EE4swapERS6_");
+@@ -61,14 +66,19 @@ asm (".hidden _ZTSSt19_Sp_make_shared_tag");
+ asm (".hidden _ZTSSt23_Sp_counted_ptr_inplaceINSt10filesystem16filesystem_error5_ImplESaIS2_ELN9__gnu_cxx12_Lock_policyE2EE");
+ asm (".hidden _ZTVSt23_Sp_counted_ptr_inplaceINSt10filesystem16filesystem_error5_ImplESaIS2_ELN9__gnu_cxx12_Lock_policyE2EE");
+ asm (".hidden _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag");
++#endif
+ asm (".hidden _ZNSt10filesystem16filesystem_error5_Impl9make_whatESt17basic_string_viewIcSt11char_traitsIcEEPKNS_4pathES8_");
+ asm (".hidden _ZNSt10unique_ptrINSt10filesystem4path5_List5_ImplENS2_13_Impl_deleterEED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt10unique_ptrINSt10filesystem4path5_List5_ImplENS2_13_Impl_deleterEED2Ev");
++#endif
+ asm (".hidden _ZNSt12system_errorC1ESt10error_codeRKSs");
++#ifndef __riscv
+ asm (".hidden _ZNSt12system_errorC2ESt10error_codeRKSs");
+ asm (".hidden _ZNSt15__allocated_ptrISaISt23_Sp_counted_ptr_inplaceINSt10filesystem16filesystem_error5_ImplESaIS3_ELN9__gnu_cxx12_Lock_policyE2EEEED1Ev");
+ asm (".hidden _ZNSt15__allocated_ptrISaISt23_Sp_counted_ptr_inplaceINSt10filesystem16filesystem_error5_ImplESaIS3_ELN9__gnu_cxx12_Lock_policyE2EEEED2Ev");
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt10filesystem16filesystem_error5_ImplESaIS2_ELN9__gnu_cxx12_Lock_policyE2EED2Ev");
++#endif
+ asm (".hidden _ZNSt10filesystem4path10_S_convertIwEEDaPKT_S4_");
+ asm (".hidden _ZNSt10filesystem8__detail24__throw_conversion_errorEv");
+ //asm (".hidden _ZTIZNSt10filesystem4path10_S_convertIwEEDaPKT_S4_E5_UCvt");
+@@ -80,7 +90,9 @@ asm (".hidden _ZNSt10filesystem8__detail24__throw_conversion_errorEv");
+ asm (".hidden _ZNKSt10filesystem4path5_List5_Impl4copyEv");
+ //asm (".hidden _ZNSs6appendERKSs");
+ #ifndef __i386__
++#ifndef __riscv
+ asm (".hidden _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv");
++#endif
+ asm (".hidden _ZNSbIwSt11char_traitsIwESaIwEE6resizeEmw");
+ asm (".hidden _ZNSbIwSt11char_traitsIwESaIwEE7reserveEm");
+ asm (".hidden _ZNSbIwSt11char_traitsIwESaIwEE9_M_mutateEmmm");
+@@ -89,8 +101,10 @@ asm (".hidden _ZNSs6resizeEmc");
+ asm (".hidden _ZNSs7reserveEm");
+ asm (".hidden _ZNSs9_M_mutateEmmm");
+ asm (".hidden _ZNSsC1ERKSsmm");
++#ifndef __riscv
+ asm (".hidden _ZNSsC2ERKSsmm");
+ asm (".hidden _ZNSt10filesystem4pathD2Ev");
++#endif
+ asm (".hidden _ZSt16__do_str_codecvtISbIwSt11char_traitsIwESaIwEEcSt7codecvtIwc11__mbstate_tES5_MS6_KFNSt12codecvt_base6resultERS5_PKcSB_RSB_PwSD_RSD_EEbPKT0_SJ_RT_RKT1_RT2_RmT3_");
+ //asm (".hidden _ZSt16__do_str_codecvtISswSt7codecvtIwc11__mbstate_tES1_MS2_KFNSt12codecvt_base6resultERS1_PKwS7_RS7_PcS9_RS9_EEbPKT0_SF_RT_RKT1_RT2_RmT3_");
+ #endif
+@@ -116,9 +130,12 @@ asm (".hidden _ZSt16__do_str_codecvtISbIwSt11char_traitsIwESaIwEEcSt7codecvtIwc1
+ #endif
+ asm (".hidden _ZNSt10filesystem4path8_CodecvtIwED0Ev");
+ asm (".hidden _ZNSt10filesystem4path8_CodecvtIwED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt10filesystem4path8_CodecvtIwED2Ev");
++#endif
+ asm (".hidden _ZNSt12codecvt_utf8IwLm1114111ELSt12codecvt_mode0EED0Ev");
+ asm (".hidden _ZNSt12codecvt_utf8IwLm1114111ELSt12codecvt_mode0EED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt12codecvt_utf8IwLm1114111ELSt12codecvt_mode0EED2Ev");
+ asm (".hidden _ZTINSt10filesystem4path8_CodecvtIwEE");
+ asm (".hidden _ZTISt12codecvt_utf8IwLm1114111ELSt12codecvt_mode0EE");
+@@ -126,6 +143,7 @@ asm (".hidden _ZTSNSt10filesystem4path8_CodecvtIwEE");
+ asm (".hidden _ZTSSt12codecvt_utf8IwLm1114111ELSt12codecvt_mode0EE");
+ asm (".hidden _ZTVNSt10filesystem4path8_CodecvtIwEE");
+ asm (".hidden _ZTVSt12codecvt_utf8IwLm1114111ELSt12codecvt_mode0EE");
++#endif
+ //asm (".hidden _ZNSt12_Destroy_auxILb0EE9__destroyIPNSt10filesystem4path5_CmptEEEvT_S6_");
+ //asm (".hidden _ZNSt10filesystem4path5_CmptD1Ev");
+ //asm (".hidden _ZNSt10filesystem4path5_CmptD2Ev");
+diff --git a/libstdc++-v3/src/nonshared17/cow-string-inst110.cc b/libstdc++-v3/src/nonshared17/cow-string-inst110.cc
+index 26bb5d6ef..f24d16381 100644
+--- a/libstdc++-v3/src/nonshared17/cow-string-inst110.cc
++++ b/libstdc++-v3/src/nonshared17/cow-string-inst110.cc
+@@ -21,16 +21,24 @@
+ // <http://www.gnu.org/licenses/>.
+ 
+ #include "../c++17/cow-string-inst.cc"
++#ifndef __riscv
+ asm (".hidden _ZNSsC2ENSs12__sv_wrapperERKSaIcE");
++#endif
+ asm (".hidden _ZNSsC1ENSs12__sv_wrapperERKSaIcE");
++#ifndef __riscv
+ asm (".hidden _ZNSs12__sv_wrapperC2ESt17basic_string_viewIcSt11char_traitsIcEE");
++#endif
+ asm (".hidden _ZNSs12__sv_wrapperC1ESt17basic_string_viewIcSt11char_traitsIcEE");
+ asm (".hidden _ZNSs17_S_to_string_viewESt17basic_string_viewIcSt11char_traitsIcEE");
+ asm (".hidden _ZNKSscvSt17basic_string_viewIcSt11char_traitsIcEEEv");
+ asm (".hidden _ZNSs4dataEv");
++#ifndef __riscv
+ asm (".hidden _ZNSbIwSt11char_traitsIwESaIwEEC2ENS2_12__sv_wrapperERKS1_");
++#endif
+ asm (".hidden _ZNSbIwSt11char_traitsIwESaIwEEC1ENS2_12__sv_wrapperERKS1_");
++#ifndef __riscv
+ asm (".hidden _ZNSbIwSt11char_traitsIwESaIwEE12__sv_wrapperC2ESt17basic_string_viewIwS0_E");
++#endif
+ asm (".hidden _ZNSbIwSt11char_traitsIwESaIwEE12__sv_wrapperC1ESt17basic_string_viewIwS0_E");
+ asm (".hidden _ZNSbIwSt11char_traitsIwESaIwEE17_S_to_string_viewESt17basic_string_viewIwS0_E");
+ asm (".hidden _ZNKSbIwSt11char_traitsIwESaIwEEcvSt17basic_string_viewIwS0_EEv");
+diff --git a/libstdc++-v3/src/nonshared17/floating_from_chars.cc b/libstdc++-v3/src/nonshared17/floating_from_chars.cc
+index b82540753..4ef0871a4 100644
+--- a/libstdc++-v3/src/nonshared17/floating_from_chars.cc
++++ b/libstdc++-v3/src/nonshared17/floating_from_chars.cc
+@@ -45,5 +45,7 @@ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcENSt3pmr21polymorphi
+ #else
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcENSt3pmr21polymorphic_allocatorIcEEE15_M_replace_coldEPcmPKcmm");
+ #endif
++#ifndef __riscv
+ asm (".hidden _ZNSt8__detail31__from_chars_alnum_to_val_tableILb0EE5valueE");
++#endif
+ asm (".hidden _ZSt10from_charsIiLi0EESt17from_chars_resultPKcS2_RT_i");
+diff --git a/libstdc++-v3/src/nonshared17/floating_from_chars110.cc b/libstdc++-v3/src/nonshared17/floating_from_chars110.cc
+index c687e0e3e..3c7cd9610 100644
+--- a/libstdc++-v3/src/nonshared17/floating_from_chars110.cc
++++ b/libstdc++-v3/src/nonshared17/floating_from_chars110.cc
+@@ -32,5 +32,7 @@ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcENSt3pmr21polymorphi
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcENSt3pmr21polymorphic_allocatorIcEEE15_M_replace_coldEPcmPKcmm");
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcENSt3pmr21polymorphic_allocatorIcEEE9_M_mutateEmmPKcm");
+ #endif
++#ifndef __riscv
+ asm (".hidden _ZNSt8__detail31__from_chars_alnum_to_val_tableILb0EE5valueE");
++#endif
+ asm (".hidden _ZSt10from_charsIiLi0EESt17from_chars_resultPKcS2_RT_i");
+diff --git a/libstdc++-v3/src/nonshared17/floating_to_chars110.cc b/libstdc++-v3/src/nonshared17/floating_to_chars110.cc
+index ff2c57c5c..de9465513 100644
+--- a/libstdc++-v3/src/nonshared17/floating_to_chars110.cc
++++ b/libstdc++-v3/src/nonshared17/floating_to_chars110.cc
+@@ -24,7 +24,9 @@
+ #include "../c++17/floating_to_chars.cc"
+ //asm (".hidden _ZSt12__to_chars_iIoENSt9enable_ifIXsrSt5__or_IJS1_IJSt7is_sameINSt9remove_cvIT_E4typeEaES2_IS6_sES2_IS6_iES2_IS6_lES2_IS6_xES2_IS6_nEEES1_IJS2_IS6_hES2_IS6_tES2_IS6_jES2_IS6_mES2_IS6_yES2_IS6_oEEES2_IcS6_EEE5valueESt15to_chars_resultE4typeEPcSQ_S4_i");
+ //asm (".hidden _ZSt12__to_chars_iIoENSt9enable_ifIXsrSt5__or_IIS1_IISt7is_sameINSt9remove_cvIT_E4typeEaES2_IS6_sES2_IS6_iES2_IS6_lES2_IS6_xES2_IS6_nEEES1_IIS2_IS6_hES2_IS6_tES2_IS6_jES2_IS6_mES2_IS6_yES2_IS6_oEEES2_IcS6_EEE5valueESt15to_chars_resultE4typeEPcSQ_S4_i");
++#ifndef __riscv
+ asm (".hidden _ZNSt8__detail18__to_chars_10_implIjEEvPcjT_");
++#endif
+ #if !defined(__i386__)
+ asm (".hidden _ZSt12__to_chars_iIoESt15to_chars_resultPcS1_T_i");
+ #endif
+diff --git a/libstdc++-v3/src/nonshared17/fs_dir.cc b/libstdc++-v3/src/nonshared17/fs_dir.cc
+index e73ae6bee..655b04794 100644
+--- a/libstdc++-v3/src/nonshared17/fs_dir.cc
++++ b/libstdc++-v3/src/nonshared17/fs_dir.cc
+@@ -21,6 +21,7 @@
+ // <http://www.gnu.org/licenses/>.
+ 
+ #include "../c++17/fs_dir.cc"
++#ifndef __riscv
+ asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem7__cxx1128recursive_directory_iterator10_Dir_stackELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info");
+ asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem7__cxx1128recursive_directory_iterator10_Dir_stackELN9__gnu_cxx12_Lock_policyE2EE3getEv");
+ asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem7__cxx1128recursive_directory_iterator10_Dir_stackELN9__gnu_cxx12_Lock_policyE2EE6uniqueEv");
+@@ -30,16 +31,20 @@ asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem7__cxx114_DirELN9__gnu_cxx12_L
+ asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem7__cxx114_DirELN9__gnu_cxx12_Lock_policyE2EE3getEv");
+ asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem7__cxx114_DirELN9__gnu_cxx12_Lock_policyE2EE6uniqueEv");
+ asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem7__cxx114_DirELN9__gnu_cxx12_Lock_policyE2EE9use_countEv");
++#endif
+ //asm (".hidden _ZNKSt12__shared_ptrINSt10filesystem7__cxx114_DirELN9__gnu_cxx12_Lock_policyE2EEcvbEv");
+ asm (".hidden _ZNSt10filesystem7__cxx114_Dir7advanceEbRSt10error_code");
+ asm (".hidden _ZNSt10filesystem7__cxx114_DirD1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt10filesystem7__cxx114_DirD2Ev");
++#endif
+ #ifdef __x86_64__
+ asm (".hidden _ZNSt10filesystem9_Dir_base7advanceEbRSt10error_code");
+ //asm (".hidden _ZNSt10filesystem9_Dir_baseC1EPKcbRSt10error_code");
+ //asm (".hidden _ZNSt10filesystem9_Dir_baseC2EPKcbRSt10error_code");
+ #endif
+ asm (".hidden _ZNSt10filesystem7__cxx114pathC1INSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES1_EERKT_NS1_6formatE");
++#ifndef __riscv
+ asm (".hidden _ZNSt10filesystem7__cxx114pathC2INSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES1_EERKT_NS1_6formatE");
+ asm (".hidden _ZNSt12__shared_ptrINSt10filesystem7__cxx1128recursive_directory_iterator10_Dir_stackELN9__gnu_cxx12_Lock_policyE2EE4swapERS6_");
+ asm (".hidden _ZNSt12__shared_ptrINSt10filesystem7__cxx1128recursive_directory_iterator10_Dir_stackELN9__gnu_cxx12_Lock_policyE2EE5resetEv");
+@@ -65,14 +70,20 @@ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt10filesystem7__cxx114_DirESaIS2_
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt10filesystem7__cxx114_DirESaIS2_ELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info");
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt10filesystem7__cxx114_DirESaIS2_ELN9__gnu_cxx12_Lock_policyE2EED0Ev");
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt10filesystem7__cxx114_DirESaIS2_ELN9__gnu_cxx12_Lock_policyE2EED1Ev");
++#endif
+ asm (".hidden _ZNSt5dequeINSt10filesystem7__cxx114_DirESaIS2_EE12emplace_backIIS2_EEERS2_DpOT_");
++#ifndef __riscv
+ asm (".hidden _ZNSt5dequeINSt10filesystem7__cxx114_DirESaIS2_EE12emplace_backIJS2_EEERS2_DpOT_");
++#endif
+ //asm (".hidden _ZNSt5dequeINSt10filesystem7__cxx114_DirESaIS2_EE16_M_push_back_auxIIRP11__dirstreamRKNS1_4pathEEEEvDpOT_");
+ //asm (".hidden _ZNSt5dequeINSt10filesystem7__cxx114_DirESaIS2_EE16_M_push_back_auxIJRP11__dirstreamRKNS1_4pathEEEEvDpOT_");
+ asm (".hidden _ZNSt5dequeINSt10filesystem7__cxx114_DirESaIS2_EED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt5dequeINSt10filesystem7__cxx114_DirESaIS2_EED2Ev");
++#endif
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_");
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_");
++#ifndef __riscv
+ asm (".hidden _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE");
+ asm (".hidden _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE");
+ asm (".hidden _ZTISt23_Sp_counted_ptr_inplaceINSt10filesystem7__cxx1128recursive_directory_iterator10_Dir_stackESaIS3_ELN9__gnu_cxx12_Lock_policyE2EE");
+@@ -87,12 +98,15 @@ asm (".hidden _ZTVSt23_Sp_counted_ptr_inplaceINSt10filesystem7__cxx114_DirESaIS2
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt10filesystem7__cxx1128recursive_directory_iterator10_Dir_stackESaIS3_ELN9__gnu_cxx12_Lock_policyE2EED2Ev");
+ asm (".hidden _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag");
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt10filesystem7__cxx114_DirESaIS2_ELN9__gnu_cxx12_Lock_policyE2EED2Ev");
+-#ifndef __i386__
++#endif
++#if !defined__i386__ && !defined __riscv
+ asm (".hidden _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv");
+ //asm (".hidden _ZNSt5dequeINSt10filesystem7__cxx114_DirESaIS2_EE17_M_reallocate_mapEmb");
+ #endif
+ asm (".hidden _ZNSt10unique_ptrINSt10filesystem7__cxx114path5_List5_ImplENS3_13_Impl_deleterEED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt10unique_ptrINSt10filesystem7__cxx114path5_List5_ImplENS3_13_Impl_deleterEED2Ev");
++#endif
+ #ifdef __i386__
+ asm (".hidden _ZNSt10filesystem9_Dir_base7advanceEbRSt10error_code");
+ #endif
+diff --git a/libstdc++-v3/src/nonshared17/fs_ops80.cc b/libstdc++-v3/src/nonshared17/fs_ops80.cc
+index eed139f91..9035d3f77 100644
+--- a/libstdc++-v3/src/nonshared17/fs_ops80.cc
++++ b/libstdc++-v3/src/nonshared17/fs_ops80.cc
+@@ -23,27 +23,37 @@
+ #include "../c++17/fs_ops.cc"
+ asm (".hidden _ZN9__gnu_cxx13stdio_filebufIcSt11char_traitsIcEED0Ev");
+ asm (".hidden _ZN9__gnu_cxx13stdio_filebufIcSt11char_traitsIcEED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZN9__gnu_cxx13stdio_filebufIcSt11char_traitsIcEED2Ev");
++#endif
+ asm (".hidden _ZNSt10filesystem12do_copy_fileEPKcS1_NS_26copy_options_existing_fileEP4statS4_RSt10error_code");
++#ifndef __riscv
+ asm (".hidden _ZNSt15_Sp_counted_ptrIDnLN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv");
+ asm (".hidden _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv");
+ asm (".hidden _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv");
++#endif
+ //asm (".hidden _ZNSt5dequeINSt10filesystem7__cxx114pathESaIS2_EE16_M_push_back_auxIJRKS2_EEEvDpOT_");
+ //asm (".hidden _ZNSt5dequeINSt10filesystem7__cxx114pathESaIS2_EE16_M_push_back_auxIIRKS2_EEEvDpOT_");
+ asm (".hidden _ZNSt5dequeINSt10filesystem7__cxx114pathESaIS2_EED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt5dequeINSt10filesystem7__cxx114pathESaIS2_EED2Ev");
+ asm (".hidden _ZTIN9__gnu_cxx13stdio_filebufIcSt11char_traitsIcEEE");
+ asm (".hidden _ZTSN9__gnu_cxx13stdio_filebufIcSt11char_traitsIcEEE");
+ asm (".hidden _ZTVN9__gnu_cxx13stdio_filebufIcSt11char_traitsIcEEE");
++#endif
+ asm (".hidden _ZNKSt10filesystem7__cxx114path8filenameEv");
+ asm (".hidden _ZNSt10unique_ptrINSt10filesystem7__cxx114path5_List5_ImplENS3_13_Impl_deleterEED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt10unique_ptrINSt10filesystem7__cxx114path5_List5_ImplENS3_13_Impl_deleterEED2Ev");
++#endif
+ asm (".hidden _ZSt14__copy_move_a1ILb1EPNSt10filesystem7__cxx114pathES2_EN9__gnu_cxx11__enable_ifIXsrSt23__is_random_access_iterIT0_NSt15iterator_traitsIS7_E17iterator_categoryEE7__valueESt15_Deque_iteratorIT1_RSD_PSD_EE6__typeES7_S7_SG_");
+ asm (".hidden _ZSt23__copy_move_backward_a1ILb1EPNSt10filesystem7__cxx114pathES2_EN9__gnu_cxx11__enable_ifIXsrSt23__is_random_access_iterIT0_NSt15iterator_traitsIS7_E17iterator_categoryEE7__valueESt15_Deque_iteratorIT1_RSD_PSD_EE6__typeES7_S7_SG_");
+ //asm (".hidden _ZSt8_DestroyISt15_Deque_iteratorINSt10filesystem7__cxx114pathERS3_PS3_EEvT_S7_");
+ #ifndef __i386__
+ asm (".hidden _ZN9__gnu_cxx13stdio_filebufIcSt11char_traitsIcEEC1EiSt13_Ios_Openmodem");
++#ifndef __riscv
+ asm (".hidden _ZN9__gnu_cxx13stdio_filebufIcSt11char_traitsIcEEC2EiSt13_Ios_Openmodem");
++#endif
+ asm (".hidden _ZNSt10filesystem8do_spaceEPKcRmS2_S2_RSt10error_code");
+ asm (".hidden _ZNSt11_Deque_baseINSt10filesystem7__cxx114pathESaIS2_EE17_M_initialize_mapEm");
+ asm (".hidden _ZNSt5dequeINSt10filesystem7__cxx114pathESaIS2_EE13_M_insert_auxINS2_8iteratorEEEvSt15_Deque_iteratorIS2_RS2_PS2_ET_SB_m");
+diff --git a/libstdc++-v3/src/nonshared17/fs_path80.cc b/libstdc++-v3/src/nonshared17/fs_path80.cc
+index 0100106a3..16576bbd3 100644
+--- a/libstdc++-v3/src/nonshared17/fs_path80.cc
++++ b/libstdc++-v3/src/nonshared17/fs_path80.cc
+@@ -21,18 +21,23 @@
+ // <http://www.gnu.org/licenses/>.
+ 
+ #include "../c++17/fs_path.cc"
++#ifndef __riscv
+ asm (".hidden _ZNKSt12__shared_ptrIKNSt10filesystem7__cxx1116filesystem_error5_ImplELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info");
+ asm (".hidden _ZNKSt12__shared_ptrIKNSt10filesystem7__cxx1116filesystem_error5_ImplELN9__gnu_cxx12_Lock_policyE2EE3getEv");
+ asm (".hidden _ZNKSt12__shared_ptrIKNSt10filesystem7__cxx1116filesystem_error5_ImplELN9__gnu_cxx12_Lock_policyE2EE6uniqueEv");
+ asm (".hidden _ZNKSt12__shared_ptrIKNSt10filesystem7__cxx1116filesystem_error5_ImplELN9__gnu_cxx12_Lock_policyE2EE9use_countEv");
+ asm (".hidden _ZNKSt12__shared_ptrIKNSt10filesystem7__cxx1116filesystem_error5_ImplELN9__gnu_cxx12_Lock_policyE2EEcvbEv");
++#endif
+ asm (".hidden _ZNKSt23__codecvt_abstract_baseIwc11__mbstate_tE2inERS0_PKcS4_RS4_PwS6_RS6_");
+ asm (".hidden _ZNKSt23__codecvt_abstract_baseIwc11__mbstate_tE3outERS0_PKwS4_RS4_PcS6_RS6_");
++#ifndef __riscv
+ asm (".hidden _ZNSt10filesystem7__cxx114path19preferred_separatorE");
++#endif
+ asm (".hidden _ZNSt10filesystem7__cxx114path5_List5clearEv");
+ asm (".hidden _ZNSt10filesystem7__cxx114path5_List5_Impl13_M_erase_fromEPKNS1_5_CmptE");
+ asm (".hidden _ZNSt10filesystem7__cxx114path5_List7reserveEib");
+ asm (".hidden _ZNSt10filesystem7__cxx114path5_ListaSERKS2_");
++#ifndef __riscv
+ asm (".hidden _ZNSt10filesystem7__cxx114path5_ListC2ERKS2_");
+ asm (".hidden _ZNSt10filesystem7__cxx114path5_ListC2Ev");
+ asm (".hidden _ZNSt12__shared_ptrIKNSt10filesystem7__cxx1116filesystem_error5_ImplELN9__gnu_cxx12_Lock_policyE2EE4swapERS7_");
+@@ -62,13 +67,18 @@ asm (".hidden _ZTSSt19_Sp_make_shared_tag");
+ asm (".hidden _ZTSSt23_Sp_counted_ptr_inplaceINSt10filesystem7__cxx1116filesystem_error5_ImplESaIS3_ELN9__gnu_cxx12_Lock_policyE2EE");
+ asm (".hidden _ZTVSt23_Sp_counted_ptr_inplaceINSt10filesystem7__cxx1116filesystem_error5_ImplESaIS3_ELN9__gnu_cxx12_Lock_policyE2EE");
+ asm (".hidden _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag");
++#endif
+ asm (".hidden _ZNSt10filesystem7__cxx1116filesystem_error5_Impl9make_whatESt17basic_string_viewIcSt11char_traitsIcEEPKNS0_4pathES9_");
+ asm (".hidden _ZNSt10filesystem7__cxx114path5_CmptD1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt10filesystem7__cxx114path5_CmptD2Ev");
++#endif
+ asm (".hidden _ZNSt10unique_ptrINSt10filesystem7__cxx114path5_List5_ImplENS3_13_Impl_deleterEED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt10unique_ptrINSt10filesystem7__cxx114path5_List5_ImplENS3_13_Impl_deleterEED2Ev");
+ asm (".hidden _ZNSt15__allocated_ptrISaISt23_Sp_counted_ptr_inplaceINSt10filesystem7__cxx1116filesystem_error5_ImplESaIS4_ELN9__gnu_cxx12_Lock_policyE2EEEED1Ev");
+ asm (".hidden _ZNSt15__allocated_ptrISaISt23_Sp_counted_ptr_inplaceINSt10filesystem7__cxx1116filesystem_error5_ImplESaIS4_ELN9__gnu_cxx12_Lock_policyE2EEEED2Ev");
++#endif
+ #if !defined (__aarch64__) && !defined (__x86_64__)
+ #ifndef __i386__
+ //asm (".hidden _ZNSt10filesystem7__cxx114pathaSISt17basic_string_viewIcSt11char_traitsIcEEEERNSt9enable_ifIXsrSt6__and_IISt6__not_ISt7is_sameINSt9remove_cvIT_E4typeES1_EES9_ISt7is_voidINSt14remove_pointerISC_E4typeEEENS0_8__detail20__constructible_fromISC_vEEEE5valueES1_E4typeERKSC_");
+@@ -91,15 +101,21 @@ asm (".hidden _ZNKSt10filesystem7__cxx114path5_List5_Impl4copyEv");
+ asm (".hidden _ZNSt10filesystem7__cxx114path7_Parser4nextEv");
+ asm (".hidden _ZNSt10filesystem7__cxx114path10_S_convertIwEEDaPKT_S5_"); // bad ppc64le
+ #endif
++#ifndef __riscv
+ asm (".hidden _ZNSt10filesystem7__cxx114path8_CodecvtIwED2Ev");
++#endif
+ asm (".hidden _ZNSt10filesystem7__cxx114path8_CodecvtIwED1Ev");
+ asm (".hidden _ZNSt10filesystem7__cxx114path8_CodecvtIwED0Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt12system_errorC2ESt10error_codeRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE");
++#endif
+ asm (".hidden _ZNSt12system_errorC1ESt10error_codeRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE");
+ asm (".hidden _ZNSt10filesystem7__cxx114path10_S_convertIwEEDaPKT_S5_");
++#ifndef __riscv
+ asm (".hidden _ZTVNSt10filesystem7__cxx114path8_CodecvtIwEE");
+ asm (".hidden _ZTSNSt10filesystem7__cxx114path8_CodecvtIwEE");
+ asm (".hidden _ZTINSt10filesystem7__cxx114path8_CodecvtIwEE");
++#endif
+ asm (".hidden _ZNSt10filesystem7__cxx118__detail24__throw_conversion_errorEv");
+ //asm (".hidden _ZTIZNSt10filesystem7__cxx114path10_S_convertIwEEDaPKT_S5_E5_UCvt");
+ //asm (".hidden _ZTSZNSt10filesystem7__cxx114path10_S_convertIwEEDaPKT_S5_E5_UCvt");
+@@ -108,7 +124,9 @@ asm (".hidden _ZNSt10filesystem7__cxx118__detail24__throw_conversion_errorEv");
+ //asm (".hidden _ZZNSt10filesystem7__cxx114path10_S_convertIwEEDaPKT_S5_EN5_UCvtD1Ev");
+ //asm (".hidden _ZZNSt10filesystem7__cxx114path10_S_convertIwEEDaPKT_S5_EN5_UCvtD2Ev");
+ asm (".hidden _ZNSt12system_errorC1ESt10error_codeRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE");
++#ifndef __riscv
+ asm (".hidden _ZNSt12system_errorC2ESt10error_codeRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE");
++#endif
+ //asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_assignERKS4_");
+ asm (".hidden _ZNSt10filesystem7__cxx114path5_List5beginEv");
+ #ifndef __i386__
+@@ -118,7 +136,9 @@ asm (".hidden _ZNSt10filesystem7__cxx114path5_List5beginEv");
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6resizeEmc");
+ //asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm");
+ //asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm");
++#ifndef __riscv
+ //asm (".hidden _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv");
++#endif
+ //asm (".hidden _ZNSt12_Destroy_auxILb0EE9__destroyIPNSt10filesystem7__cxx114path5_CmptEEEvT_S7_");
+ asm (".hidden _ZNKSt10filesystem7__cxx114path5_List5_Impl4copyEv");
+ #endif
+@@ -142,9 +162,12 @@ asm (".hidden _ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE6resizeEjw");
+ #endif
+ asm (".hidden _ZNSt10filesystem7__cxx114path8_CodecvtIwED0Ev");
+ asm (".hidden _ZNSt10filesystem7__cxx114path8_CodecvtIwED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt10filesystem7__cxx114path8_CodecvtIwED2Ev");
++#endif
+ //asm (".hidden _ZNSt12codecvt_utf8IwLm1114111ELSt12codecvt_mode0EED0Ev");
+ //asm (".hidden _ZNSt12codecvt_utf8IwLm1114111ELSt12codecvt_mode0EED1Ev");
++#ifndef __riscv
+ //asm (".hidden _ZNSt12codecvt_utf8IwLm1114111ELSt12codecvt_mode0EED2Ev");
+ asm (".hidden _ZTINSt10filesystem7__cxx114path8_CodecvtIwEE");
+ //asm (".hidden _ZTISt12codecvt_utf8IwLm1114111ELSt12codecvt_mode0EE");
+@@ -152,6 +175,9 @@ asm (".hidden _ZTSNSt10filesystem7__cxx114path8_CodecvtIwEE");
+ //asm (".hidden _ZTSSt12codecvt_utf8IwLm1114111ELSt12codecvt_mode0EE");
+ asm (".hidden _ZTVNSt10filesystem7__cxx114path8_CodecvtIwEE");
+ //asm (".hidden _ZTVSt12codecvt_utf8IwLm1114111ELSt12codecvt_mode0EE");
++#endif
+ asm (".hidden _ZNSt10filesystem7__cxx114path10_S_convertIwEEDaPKT_S5_");
++#ifndef __riscv
+ asm (".hidden _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag");
+ asm (".hidden _ZNSt10filesystem7__cxx114path19preferred_separatorE");
++#endif
+diff --git a/libstdc++-v3/src/nonshared17/memory_resource.cc b/libstdc++-v3/src/nonshared17/memory_resource.cc
+index b94792bd5..36bfac568 100644
+--- a/libstdc++-v3/src/nonshared17/memory_resource.cc
++++ b/libstdc++-v3/src/nonshared17/memory_resource.cc
+@@ -26,20 +26,28 @@ asm (".hidden _ZNKSt3pmr28unsynchronized_pool_resource11do_is_equalERKNS_15memor
+ asm (".hidden _ZNSt3pmr15__pool_resource14_M_alloc_poolsEv");
+ asm (".hidden _ZNSt3pmr15__pool_resource7releaseEv");
+ asm (".hidden _ZNSt3pmr15__pool_resourceC1ERKNS_12pool_optionsEPNS_15memory_resourceE");
++#ifndef __riscv
+ asm (".hidden _ZNSt3pmr15__pool_resourceC2ERKNS_12pool_optionsEPNS_15memory_resourceE");
++#endif
+ asm (".hidden _ZNSt3pmr15__pool_resourceD1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt3pmr15__pool_resourceD2Ev");
++#endif
+ asm (".hidden _ZNSt3pmr26synchronized_pool_resource15_M_alloc_tpoolsERSt10lock_guardISt12shared_mutexE");
+ asm (".hidden _ZNSt3pmr26synchronized_pool_resource22_M_alloc_shared_tpoolsERSt10lock_guardISt12shared_mutexE");
+ asm (".hidden _ZNSt3pmr26synchronized_pool_resource24_M_thread_specific_poolsEv");
+ asm (".hidden _ZNSt3pmr26synchronized_pool_resource7_TPoolsD1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt3pmr26synchronized_pool_resource7_TPoolsD2Ev");
++#endif
+ asm (".hidden _ZNSt3pmr26synchronized_pool_resourceD0Ev");
+ asm (".hidden _ZNSt3pmr28unsynchronized_pool_resourceD0Ev");
++#ifndef __riscv
+ asm (".hidden _ZTSNSt3pmr26synchronized_pool_resourceE");
+ asm (".hidden _ZTSNSt3pmr28unsynchronized_pool_resourceE");
+ asm (".hidden _ZTVNSt3pmr26synchronized_pool_resourceE");
+ asm (".hidden _ZTVNSt3pmr28unsynchronized_pool_resourceE");
++#endif
+ asm (".hidden _ZNKSt3pmr25monotonic_buffer_resource11do_is_equalERKNS_15memory_resourceE");
+ asm (".hidden _ZNSt3pmr15__pool_resource5_Pool12try_allocateEv");
+ asm (".hidden _ZNSt3pmr15__pool_resource5_Pool9replenishEPNS_15memory_resourceERKNS_12pool_optionsE");
+@@ -71,5 +79,7 @@ asm (".hidden _ZNSt6vectorINSt3pmr15__pool_resource9_BigBlockENS0_21polymorphic_
+ asm (".hidden _ZNSt6vectorINSt3pmr15__pool_resource9_BigBlockENS0_21polymorphic_allocatorIS2_EEE17_M_realloc_appendIJRjS7_EEEvDpOT_");
+ #else
+ asm (".hidden _ZNSt6vectorINSt3pmr15__pool_resource9_BigBlockENS0_21polymorphic_allocatorIS2_EEE17_M_realloc_appendIIRmS7_EEEvDpOT_");
++#ifndef __riscv
+ asm (".hidden _ZNSt6vectorINSt3pmr15__pool_resource9_BigBlockENS0_21polymorphic_allocatorIS2_EEE17_M_realloc_appendIJRmS7_EEEvDpOT_");
+ #endif
++#endif
+diff --git a/libstdc++-v3/src/nonshared17/string-inst110.cc b/libstdc++-v3/src/nonshared17/string-inst110.cc
+index a317ca76e..a3c6d1900 100644
+--- a/libstdc++-v3/src/nonshared17/string-inst110.cc
++++ b/libstdc++-v3/src/nonshared17/string-inst110.cc
+@@ -21,16 +21,24 @@
+ // <http://www.gnu.org/licenses/>.
+ 
+ #include "../c++17/string-inst.cc"
++#ifndef __riscv
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ENS4_12__sv_wrapperERKS3_");
++#endif
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1ENS4_12__sv_wrapperERKS3_");
++#ifndef __riscv
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12__sv_wrapperC2ESt17basic_string_viewIcS2_E");
++#endif
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12__sv_wrapperC1ESt17basic_string_viewIcS2_E");
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE17_S_to_string_viewESt17basic_string_viewIcS2_E");
+ asm (".hidden _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEcvSt17basic_string_viewIcS2_EEv");
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4dataEv");
++#ifndef __riscv
+ asm (".hidden _ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC2ENS4_12__sv_wrapperERKS3_");
++#endif
+ asm (".hidden _ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEC1ENS4_12__sv_wrapperERKS3_");
++#ifndef __riscv
+ asm (".hidden _ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12__sv_wrapperC2ESt17basic_string_viewIwS2_E");
++#endif
+ asm (".hidden _ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE12__sv_wrapperC1ESt17basic_string_viewIwS2_E");
+ asm (".hidden _ZNSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEE17_S_to_string_viewESt17basic_string_viewIwS2_E");
+ asm (".hidden _ZNKSt7__cxx1112basic_stringIwSt11char_traitsIwESaIwEEcvSt17basic_string_viewIwS2_EEv");
+diff --git a/libstdc++-v3/src/nonshared20/tzdb110.cc b/libstdc++-v3/src/nonshared20/tzdb110.cc
+index 4be193df7..e4b54a8e9 100644
+--- a/libstdc++-v3/src/nonshared20/tzdb110.cc
++++ b/libstdc++-v3/src/nonshared20/tzdb110.cc
+@@ -24,4 +24,6 @@
+ #include "tzdb80.cc"
+ asm (".hidden _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED0Ev");
+ asm (".hidden _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED2Ev");
++#endif
+diff --git a/libstdc++-v3/src/nonshared20/tzdb80.cc b/libstdc++-v3/src/nonshared20/tzdb80.cc
+index dc123a2ae..1e88dba3b 100644
+--- a/libstdc++-v3/src/nonshared20/tzdb80.cc
++++ b/libstdc++-v3/src/nonshared20/tzdb80.cc
+@@ -23,33 +23,51 @@
+ #include "../c++20/tzdb.cc"
+ asm (".hidden _ZNKSt6chrono9time_zone4nameEv");
+ asm (".hidden _ZNKSt6chrono14time_zone_link4nameEv");
++#ifndef __riscv
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt6chrono9tzdb_list5_NodeESaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev");
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt6chrono9tzdb_list5_NodeESaIvELN9__gnu_cxx12_Lock_policyE2EED1Ev");
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt6chrono9tzdb_list5_NodeESaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev");
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt6chrono9tzdb_list5_NodeESaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv");
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt6chrono9tzdb_list5_NodeESaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info");
++#endif
+ asm (".hidden _ZNKSt6chrono14year_month_day19_M_days_since_epochEv");
+ asm (".hidden _ZNSt6chronossERKNS_14time_zone_linkES2_");
++#ifndef __riscv
+ asm (".hidden _ZNSt6chrono9time_zoneC2ESt10unique_ptrINS0_5_ImplESt14default_deleteIS2_EE");
++#endif
+ asm (".hidden _ZNSt6chrono9time_zoneC1ESt10unique_ptrINS0_5_ImplESt14default_deleteIS2_EE");
++#ifndef __riscv
+ asm (".hidden _ZNSt6chrono9tzdb_list5_Node13_S_head_cacheE");
+ asm (".hidden _ZNSt6atomicISt10shared_ptrINSt6chrono9tzdb_list5_NodeEEED2Ev");
++#endif
+ asm (".hidden _ZNSt6atomicISt10shared_ptrINSt6chrono9tzdb_list5_NodeEEED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt6chrono9tzdb_list5_Node13_S_head_ownerE");
++#endif
+ asm (".hidden _ZNSt6chrono9tzdb_list5_Node15_S_replace_headESt10shared_ptrIS1_ES3_");
+ //asm (".hidden _ZNSt6vectorISt4pairINSt6chrono8sys_infoESt17basic_string_viewIcSt11char_traitsIcEEESaIS7_EE17_M_realloc_insertIJRS2_RS6_EEEvN9__gnu_cxx17__normal_iteratorIPS7_S9_EEDpOT_");
+ //asm (".hidden _ZNSt6vectorISt4pairINSt6chrono8sys_infoESt17basic_string_viewIcSt11char_traitsIcEEESaIS7_EE17_M_realloc_insertIIRS2_RS6_EEEvN9__gnu_cxx17__normal_iteratorIPS7_S9_EEDpOT_");
++#ifndef __riscv
+ asm (".hidden _ZNSt6chrono9time_zoneD2Ev");
++#endif
+ asm (".hidden _ZNSt6chrono9time_zoneD1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt23_Sp_counted_ptr_inplaceINSt6chrono9tzdb_list5_NodeESaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv");
+ asm (".hidden _ZSt11make_uniqueINSt6chrono9time_zone5_ImplEJRSt10shared_ptrINS0_9tzdb_list5_NodeEEEENSt8__detail9_MakeUniqIT_E15__single_objectEDpOT0_");
++#endif
+ asm (".hidden _ZSt11make_uniqueINSt6chrono9time_zone5_ImplEIRSt10shared_ptrINS0_9tzdb_list5_NodeEEEENSt8__detail9_MakeUniqIT_E15__single_objectEDpOT0_");
++#ifndef __riscv
+ asm (".hidden _ZNSt6vectorINSt6chrono9time_zoneESaIS1_EE12emplace_backIJS1_EEERS1_DpOT_");
++#endif
+ asm (".hidden _ZNSt6vectorINSt6chrono9time_zoneESaIS1_EE12emplace_backIIS1_EEERS1_DpOT_");
++#ifndef __riscv
+ asm (".hidden _ZNSt12_Vector_baseINSt6chrono11leap_secondESaIS1_EED2Ev");
++#endif
+ asm (".hidden _ZNSt12_Vector_baseINSt6chrono11leap_secondESaIS1_EED1Ev");
+ asm (".hidden _ZNSt6chrono9tzdb_list5_Node20_S_read_leap_secondsEv");
++#ifndef __riscv
+ asm (".hidden _ZNSt6vectorINSt6chrono14time_zone_linkESaIS1_EE12emplace_backIJS1_EEERS1_DpOT_");
++#endif
+ asm (".hidden _ZNSt6vectorINSt6chrono14time_zone_linkESaIS1_EE12emplace_backIIS1_EEERS1_DpOT_");
+ asm (".hidden _ZSt23__atomic_notify_addressIiEvPKT_b");
+ asm (".hidden _ZSt16__insertion_sortIN9__gnu_cxx17__normal_iteratorIPNSt6chrono9time_zoneESt6vectorIS3_SaIS3_EEEENS0_5__ops15_Iter_comp_iterIZNSt6ranges8__detail16__make_comp_projINSB_4lessESt8identityEEDaRT_RT0_EUlOSG_OSI_E_EEEvSG_SG_SI_");
+@@ -58,18 +76,30 @@ asm (".hidden _ZZNSt6ranges8__detail16__make_comp_projINS_4lessEMNSt6chrono9time
+ asm (".hidden _ZSt16__insertion_sortIN9__gnu_cxx17__normal_iteratorIPNSt6chrono9time_zoneESt6vectorIS3_SaIS3_EEEENS0_5__ops15_Iter_comp_iterIZNSt6ranges8__detail16__make_comp_projINSB_4lessEMS3_KDoFSt17basic_string_viewIcSt11char_traitsIcEEvEEEDaRT_RT0_EUlOSL_OSN_E_EEEvSL_SL_SN_");
+ asm (".hidden _ZZNSt6ranges8__detail16__make_comp_projINS_4lessEMNSt6chrono14time_zone_linkEKDoFSt17basic_string_viewIcSt11char_traitsIcEEvEEEDaRT_RT0_ENKUlOSB_OSD_E_clIRS4_SJ_EEbSF_SG_");
+ asm (".hidden _ZSt16__insertion_sortIN9__gnu_cxx17__normal_iteratorIPNSt6chrono14time_zone_linkESt6vectorIS3_SaIS3_EEEENS0_5__ops15_Iter_comp_iterIZNSt6ranges8__detail16__make_comp_projINSB_4lessEMS3_KDoFSt17basic_string_viewIcSt11char_traitsIcEEvEEEDaRT_RT0_EUlOSL_OSN_E_EEEvSL_SL_SN_");
++#ifndef __riscv
+ asm (".hidden _ZSt4swapINSt6chrono9time_zoneEENSt9enable_ifIXsrSt6__and_IJSt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS6_ESt18is_move_assignableIS6_EEE5valueEvE4typeERS6_SG_");
++#endif
+ asm (".hidden _ZSt4swapINSt6chrono9time_zoneEENSt9enable_ifIXsrSt6__and_IISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS6_ESt18is_move_assignableIS6_EEE5valueEvE4typeERS6_SG_");
++#ifndef __riscv
+ asm (".hidden _ZSt4swapINSt6chrono14time_zone_linkEENSt9enable_ifIXsrSt6__and_IJSt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS6_ESt18is_move_assignableIS6_EEE5valueEvE4typeERS6_SG_");
++#endif
+ asm (".hidden _ZSt4swapINSt6chrono14time_zone_linkEENSt9enable_ifIXsrSt6__and_IISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS6_ESt18is_move_assignableIS6_EEE5valueEvE4typeERS6_SG_");
++#ifndef __riscv
+ asm (".hidden _ZTVSt23_Sp_counted_ptr_inplaceINSt6chrono9tzdb_list5_NodeESaIvELN9__gnu_cxx12_Lock_policyE2EE");
++#endif
+ asm (".hidden _ZNSt6chrono9tzdb_list5_Node12_S_init_tzdbEv");
++#ifndef __riscv
+ asm (".hidden _ZNSt6chrono9tzdb_list5_Node11_S_the_listE");
++#endif
++#ifndef __riscv
+ asm (".hidden _ZTSSt23_Sp_counted_ptr_inplaceINSt6chrono9tzdb_list5_NodeESaIvELN9__gnu_cxx12_Lock_policyE2EE");
+ asm (".hidden _ZTISt23_Sp_counted_ptr_inplaceINSt6chrono9tzdb_list5_NodeESaIvELN9__gnu_cxx12_Lock_policyE2EE");
++#endif
+ //asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev");
+ //asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2EOS4_");
++#endif
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1EOS4_");
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv");
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_assignERKS4_");
+@@ -82,7 +112,9 @@ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceE
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcj");
+ #else
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1EPKcmRKS3_");
++#ifndef __riscv
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2EPKcmRKS3_");
++#endif
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm");
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm");
+ asm (".hidden _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm");
+@@ -109,14 +141,21 @@ asm (".hidden _ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIPNSt6chrono1
+ asm (".hidden _ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIPNSt6chrono9time_zoneESt6vectorIS3_SaIS3_EEEElNS0_5__ops15_Iter_comp_iterIZNSt6ranges8__detail16__make_comp_projINSB_4lessEMS3_KDoFSt17basic_string_viewIcSt11char_traitsIcEEvEEEDaRT_RT0_EUlOSL_OSN_E_EEEvSL_SL_SN_T1_");
+ asm (".hidden _ZSt16__introsort_loopIN9__gnu_cxx17__normal_iteratorIPNSt6chrono9time_zoneESt6vectorIS3_SaIS3_EEEElNS0_5__ops15_Iter_comp_iterIZNSt6ranges8__detail16__make_comp_projINSB_4lessESt8identityEEDaRT_RT0_EUlOSG_OSI_E_EEEvSG_SG_SI_T1_");
+ #endif
++#ifndef __riscv
+ asm (".hidden _ZTSSt19_Sp_make_shared_tag");
++#endif
+ #ifndef __i386__
++#ifndef __riscv
+ asm (".hidden _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv");
+ #endif
++#endif
+ asm (".hidden _ZSt23__atomic_wait_address_vIiZNKSt13__atomic_baseIiE4waitEiSt12memory_orderEUlvE_EvPKT_S4_T0_");
++#ifndef __riscv
+ asm (".hidden _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv");
+ asm (".hidden _ZNSt10unique_ptrINSt10filesystem7__cxx114path5_List5_ImplENS3_13_Impl_deleterEED2Ev");
++#endif
+ asm (".hidden _ZNSt10unique_ptrINSt10filesystem7__cxx114path5_List5_ImplENS3_13_Impl_deleterEED1Ev");
++#ifndef __riscv
+ asm (".hidden _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE");
+ asm (".hidden _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE");
+ asm (".hidden _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE");
+@@ -124,4 +163,5 @@ asm (".hidden _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE");
+ asm (".hidden _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag");
+ asm (".hidden _ZZNSt8__detail18__waiter_pool_base6_S_forEPKvE3__w");
+ asm (".hidden _ZNSt6vectorISt4pairINSt6chrono8sys_infoESt17basic_string_viewIcSt11char_traitsIcEEESaIS7_EE17_M_realloc_appendIJRS2_RS6_EEEvDpOT_");
++#endif
+ asm (".hidden _ZNSt6vectorISt4pairINSt6chrono8sys_infoESt17basic_string_viewIcSt11char_traitsIcEEESaIS7_EE17_M_realloc_appendIIRS2_RS6_EEEvDpOT_");
+diff --git a/libstdc++-v3/src/nonshared98/extfloat.S b/libstdc++-v3/src/nonshared98/extfloat.S
+index c6270e618..b6e4164b5 100644
+--- a/libstdc++-v3/src/nonshared98/extfloat.S
++++ b/libstdc++-v3/src/nonshared98/extfloat.S
+@@ -53,8 +53,11 @@
+ #elif defined __s390__
+ #define ALIGN1	.align 4
+ #define ALIGN3	.align 2
++#elif defined __riscv && __riscv_xlen == 64
++#define ALIGN1	.align 3
++#define ALIGN3	.align 3
+ #endif
+-#if defined __x86_64__ || defined __powerpc64__ || defined __s390x__ || defined __ia64__ || defined __aarch64__
++#if defined __x86_64__ || defined __powerpc64__ || defined __s390x__ || defined __ia64__ || defined __aarch64__ || (defined __riscv && __riscv_xlen == 64)
+ #define SIZE1	32
+ #define SIZE2	16
+ #define OFF	16
+-- 
+2.43.0
+

README.md

@@ -1,23 +1,55 @@
 # gcc-14
 
 #### 介绍
-gcc multi-version toolset for openEuler
+openEuler 24.03 LTS 版本选择 GCC 12.3.1 作为开发基线，确保在整 LTS 周期内，系统版本保持相对稳定。
 
+为满足用户对不同版本编译器的需求，使能多样算力新特性，基于 openEuler 24.09 系统，推出 gcc-toolset-14 副版本编译工具链，形成主版本为 GCC12，副版本为 GCC14 的编译器搭配，为用户提供更加灵活且高效的编译选择。
 #### 软件架构
-软件架构说明
 
+```shell
+## 默认 GCC12 路径
+PATH=/usr/bin/
+## 默认动态库路径
+LD_LIBRARY_PATH=/usr/lib64/
+
+## gcc-toolset-14 副版本安装路径
+PATH=/opt/openEuler/gcc-toolset-14/root/usr/bin/
+```
+
+#### 软件约束
+
+| 名称| 版本要求|
+| --- | --- |
+| 系统版本| openEuler 24.09 以上 |
+| 默认GCC |  12.3.1 |
+| 架构 | Aarch64 / X86_64|
+| Glibc | 2.34 及以上 |
+| Binutils | 2.42 及以上|
+
+约束是指本多版本工具链在以上条件的版本中进行了完整的工程验证和兼容性测试，如果使用在其他场景中，不保证完整功能实现。
 
 #### 安装教程
 
-1.  xxxx
-2.  xxxx
-3.  xxxx
+1.  `yum install gcc-toolset-14-gcc gcc-toolset-14-g++`
+2.  如果需要搭配 binutils-2.42，则 `yum install gcc-toolset-14-binutils`
 
 #### 使用说明
 
-1.  xxxx
-2.  xxxx
-3.  xxxx
+1.  安装 scl
+> yum install scl-utils
+
+2.  注册 gcc-toolset-14
+> scl register /opt/openEuler/gcc-toolset-14/
+
+使用`scl list-collections`显示 gcc-toolset-14 已经在 scl 中注册成功；
+
+3.  切换 gcc-toolset-14
+> scl enable gcc-toolset-14 bash
+
+4.  退出 gcc-toolset-14
+> exit
+
+退出bash shell会话，此时 GCC 的版本切换成系统默认版本。
 
 #### 参与贡献
 

gcc-14.spec

@@ -36,7 +36,7 @@
 %else
 %global build_libquadmath 0
 %endif
-%ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 riscv64
+%ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 riscv64 loongarch64
 %global build_libasan 1
 %else
 %global build_libasan 0
@@ -46,33 +46,33 @@
 %else
 %global build_libhwasan 0
 %endif
-%ifarch x86_64 ppc64 ppc64le aarch64 s390x riscv64
+%ifarch x86_64 ppc64 ppc64le aarch64 s390x riscv64 loongarch64
 %global build_libtsan 1
 %else
 %global build_libtsan 0
 %endif
-%ifarch x86_64 ppc64 ppc64le aarch64 s390x riscv64
+%ifarch x86_64 ppc64 ppc64le aarch64 s390x riscv64 loongarch64
 %global build_liblsan 1
 %else
 %global build_liblsan 0
 %endif
-%ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 riscv64
+%ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 riscv64 loongarch64
 %global build_libubsan 1
 %else
 %global build_libubsan 0
 %endif
-%ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 %{mips} riscv64
+%ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 %{mips} riscv64 loongarch64
 %global build_libatomic 1
 %else
 %global build_libatomic 0
 %endif
-%ifarch %{ix86} x86_64 %{arm} alpha ppc ppc64 ppc64le ppc64p7 s390 s390x aarch64 riscv64
+%ifarch %{ix86} x86_64 %{arm} alpha ppc ppc64 ppc64le ppc64p7 s390 s390x aarch64 riscv64 loongarch64
 %global build_libitm 1
 %else
 %global build_libitm 0
 %endif
 %global build_libstdcxx_docs 0
-%ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 %{mips} riscv64
+%ifarch %{ix86} x86_64 ppc ppc64 ppc64le ppc64p7 s390 s390x %{arm} aarch64 %{mips} riscv64 loongarch64
 %global attr_ifunc 1
 %else
 %global attr_ifunc 0
@@ -90,11 +90,10 @@
 Summary: Various compilers (C, C++, Objective-C, ...)
 Name: %{?_scl_prefix}gcc%{gcc_ver}
 Version: 14.2.1
-Release: 2
+Release: 7
 # libgcc, libgfortran, libgomp, libstdc++ and crtstuff have
 # GCC Runtime Exception.
 License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD
-ExcludeArch: loongarch64
 Source0: https://ftp.gnu.org/gnu/gcc/gcc-14.2.0/gcc-14.2.0.tar.xz
 URL: http://gcc.gnu.org
 
@@ -128,7 +127,7 @@ BuildRequires: dblatex, texlive-collection-latex, docbook-style-xsl
 Requires: %{?_scl_prefix}libasan%{gcc_ver} = %{version}-%{release}
 %endif
 Requires: libgcc >= 4.1.2-43
-Requires: libgomp >= 4.4.4-13
+Requires: %{?_scl_prefix}libgomp%{gcc_ver} = %{version}-%{release}
 # lto-wrapper invokes make
 Requires: make
 AutoReq: true
@@ -172,9 +171,36 @@ Provides: %{?_scl_prefix}gcc%{gcc_ver}(major) = %{gcc_major}
 Patch1001: GCC14-1001-libstdc++-compat.patch
 Patch1002: GCC14-1002-change-gcc-version.patch
 Patch1003: GCC14-1003-i386-Add-non-optimize-prefetchi-intrins.patch
+Patch1004: GCC14-1004-riscv-lib64.patch
+Patch1005: GCC14-1005-libstdc-compat-Update-symbol-list-for-RISC-V-64.patch
 # On ARM EABI systems, we do want -gnueabi to be part of the
 # target triple.
-%global nonsharedver 48
+
+Patch3000: 0001-LoongArch-Remove-the-definition-of-the-macro-LOGICAL.patch
+Patch3001: 0002-LoongArch-Fix-mode-size-comparision-in-loongarch_exp.patch
+Patch3002: 0003-LoongArch-Use-bstrins-for-value-1u-const.patch
+Patch3003: 0004-LoongArch-Tweak-IOR-rtx_cost-for-bstrins.patch
+Patch3004: 0005-LoongArch-NFC-Dedup-and-sort-the-comment-in-loongarc.patch
+Patch3005: 0006-LoongArch-Fix-explicit-relocs-extreme-tls-desc.c-tes.patch
+Patch3006: 0007-LoongArch-Define-loongarch_insn_cost-and-set-the-cos.patch
+Patch3007: 0008-LoongArch-Remove-unreachable-codes.patch
+Patch3008: 0009-LoongArch-Organize-the-code-related-to-split-move-an.patch
+Patch3009: 0010-LoongArch-Expand-some-SImode-operations-through-si3_.patch
+Patch3010: 0011-LoongArch-Relax-ins_zero_bitmask_operand-and-remove-.patch
+Patch3011: 0012-LoongArch-Rework-bswap-hi-si-di-2-definition.patch
+Patch3012: 0013-testsuite-fix-dg-do-preprocess-typo.patch
+Patch3013: 0014-LoongArch-Remove-gawk-extension-from-a-generator-scr.patch
+Patch3014: 0015-LoongArch-Use-iorn-and-andn-standard-pattern-names.patch
+Patch3015: 0016-LoongArch-Drop-vcond-u-expanders.patch
+Patch3016: 0017-LoongArch-Provide-ashr-lshr-and-ashl-RTL-pattern-for.patch
+Patch3017: 0018-LoongArch-Implement-scalar-isinf-isnormal-and-isfini.patch
+Patch3018: 0019-LoongArch-Add-support-to-annotate-tablejump.patch
+Patch3019: 0020-LoongArch-Fix-up-r15-4130.patch
+Patch2020: 0021-LoongArch-Change-OSDIR-for-distribution.patch
+Patch3021: 0022-LoongArch-support-nonshared-extfloat.diff
+Patch3022: 0023-LoongArch-libstdcxx-nonshared.diff
+
+%global nonsharedver 80
 %ifnarch %{arm}
 %global _gnu %{nil}
 %else
@@ -273,7 +299,7 @@ Objective-C dynamically linked programs.
 Summary: Fortran support for GCC 14
 Requires: %{?_scl_prefix}gcc%{gcc_ver} = %{version}-%{release}
 %if %{build_libquadmath}
-Requires: %{?_scl_prefix}libquadmath%{gcc_ver}-devel = %{version}-%{release}
+Requires: %{?_scl_prefix}libquadmath%{gcc_ver} = %{version}-%{release}
 %endif
 Autoreq: true
 
@@ -285,19 +311,22 @@ with the GNU Compiler Collection.
 Summary: Static Fortran libraries
 Requires: %{?_scl_prefix}gcc%{gcc_ver} = %{version}-%{release}
 %if %{build_libquadmath}
-%if 0%{!?scl:1}
-Requires: libquadmath
-%endif
-Requires: %{?_scl_prefix}libquadmath%{gcc_ver}-devel = %{version}-%{release}
+Requires: %{?_scl_prefix}libquadmath%{gcc_ver} = %{version}-%{release}
 %endif
 
 %description -n %{?_scl_prefix}libgfortran%{gcc_ver}-devel
 This package contains static Fortran libraries.
 %if %{build_libquadmath}
-Requires: %{?_scl_prefix}libquadmath%{gcc_ver}-devel = %{version}-%{release}
+Requires: %{?_scl_prefix}libquadmath%{gcc_ver} = %{version}-%{release}
 %endif
 Autoreq: true
 
+%package -n %{?_scl_prefix}libgomp%{gcc_ver}
+Summary: GCC OpenMP shared support library
+
+%description -n %{?_scl_prefix}libgomp%{gcc_ver}
+This package contains GCC shared support library which is needed
+for OpenMP support.
 %package gdb-plugin
 Summary: GCC 14 plugin for GDB
 Requires: %{?_scl_prefix}gcc%{gcc_ver} = %{version}-%{release}
@@ -527,7 +556,7 @@ CONFIGURE_OPTS="\
 	--prefix=%{_prefix} --mandir=%{_mandir} --infodir=%{_infodir} \
 	--with-bugurl=https://gitee.com/src-openeuler/gcc-14/issues \
 	--enable-shared --enable-threads=posix --enable-checking=release --with-isl \
-%ifarch aarch64 riscv64
+%ifarch aarch64
 	--enable-multilib \
 %else
 	--disable-multilib \
@@ -564,6 +593,9 @@ CONFIGURE_OPTS="\
 %ifnarch sparc sparcv9 ppc
 	--build=%{gcc_target_platform} \
 %endif
+%ifarch loongarch64
+  --disable-libquadmath --enable-tls --enable-default-pie \
+%endif
 %if 0%{?scl:1}
     --program-suffix=%{binsuffix}
 %endif
@@ -717,37 +749,12 @@ TARGET_PLATFORM=%{gcc_target_platform}
 # There are some MP bugs in libstdc++ Makefiles
 make %{?_smp_mflags} -C %{gcc_target_platform}/libstdc++-v3
 
-%if 0%{?scl:1}
-rm -f gcc/libgcc_s.so
-echo '/* GNU ld script
-   Use the shared library, but some functions are only in
-   the static library, so try that secondarily.  */
-%{oformat}
-GROUP ( /%{_lib}/libgcc_s.so.1 libgcc.a )' > gcc/libgcc_s.so
-%endif
-
 make prefix=%{buildroot}%{_prefix} mandir=%{buildroot}%{_mandir} \
   infodir=%{buildroot}%{_infodir} install
 
-%if 0%{?scl:1}
-rm -f gcc/libgcc_s.so
-ln -sf libgcc_s.so.1 gcc/libgcc_s.so
-%endif
-
 FULLPATH=%{buildroot}%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}
 FULLEPATH=%{buildroot}%{_prefix}/libexec/gcc/%{gcc_target_platform}/%{gcc_major}
 
-%if 0%{?scl:1}
-ln -sf ../../../../bin/ar $FULLEPATH/ar
-ln -sf ../../../../bin/as $FULLEPATH/as
-ln -sf ../../../../bin/ld $FULLEPATH/ld
-ln -sf ../../../../bin/ld.bfd $FULLEPATH/ld.bfd
-ln -sf ../../../../bin/ld.gold $FULLEPATH/ld.gold
-ln -sf ../../../../bin/nm $FULLEPATH/nm
-ln -sf ../../../../bin/objcopy $FULLEPATH/objcopy
-ln -sf ../../../../bin/ranlib $FULLEPATH/ranlib
-ln -sf ../../../../bin/strip $FULLEPATH/strip
-%endif
 # fix some things
 ln -sf gcc %{buildroot}%{_prefix}/bin/cc
 mkdir -p %{buildroot}/lib
@@ -846,25 +853,27 @@ mkdir -p %{buildroot}/%{_lib}
 mv -f %{buildroot}%{_prefix}/%{_lib}/libgcc_s.so.1 %{buildroot}%{_prefix}/%{_lib}/libgcc_s-%{gcc_major}.so.1
 chmod 755 %{buildroot}%{_prefix}/%{_lib}/libgcc_s-%{gcc_major}.so.1
 ln -sf libgcc_s-%{gcc_major}.so.1 %{buildroot}%{_prefix}/%{_lib}/libgcc_s.so.1
-ln -sf /%{_lib}/libgcc_s.so.1 $FULLPATH/libgcc_s.so
-%ifarch %{multilib_64_archs}
-ln -sf /lib/libgcc_s.so.1 $FULLPATH/32/libgcc_s.so
-%endif
 %ifarch %{ix86} x86_64 ppc ppc64 ppc64p7 ppc64le %{arm} aarch64 riscv64
 rm -f $FULLPATH/libgcc_s.so
 echo '/* GNU ld script
    Use the shared library, but some functions are only in
    the static library, so try that secondarily.  */
 %{oformat}
-GROUP ( /%{_lib}/libgcc_s.so.1 libgcc.a )' > $FULLPATH/libgcc_s.so
+GROUP ( %{_prefix}/%{_lib}/libgcc_s.so.1 libgcc.a )' > $FULLPATH/libgcc_s.so
+%else
+ln -sf %{_prefix}/%{_lib}/libgcc_s.so.1 $FULLPATH/libgcc_s.so
 %endif
 %ifarch sparcv9 ppc
+%ifarch ppc
 rm -f $FULLPATH/64/libgcc_s.so
 echo '/* GNU ld script
    Use the shared library, but some functions are only in
    the static library, so try that secondarily.  */
 %{oformat2}
-GROUP ( /lib64/libgcc_s.so.1 libgcc.a )' > $FULLPATH/64/libgcc_s.so
+GROUP ( %{_prefix}/lib64/libgcc_s.so.1 libgcc.a )' > $FULLPATH/64/libgcc_s.so
+%else
+ln -sf %{_prefix}/lib64/libgcc_s.so.1 $FULLPATH/64/libgcc_s.so
+%endif
 %endif
 %ifarch %{multilib_64_archs}
 %ifarch x86_64 ppc64 ppc64p7
@@ -873,9 +882,9 @@ echo '/* GNU ld script
    Use the shared library, but some functions are only in
    the static library, so try that secondarily.  */
 %{oformat2}
-GROUP ( /lib/libgcc_s.so.1 libgcc.a )' > $FULLPATH/32/libgcc_s.so
+GROUP ( %{_prefix}/lib/libgcc_s.so.1 libgcc.a )' > $FULLPATH/32/libgcc_s.so
 %else
-ln -sf /lib/libgcc_s.so.1 $FULLPATH/32/libgcc_s.so
+ln -sf %{_prefix}/lib/libgcc_s.so.1 $FULLPATH/32/libgcc_s.so
 %endif
 %endif
 
@@ -918,43 +927,19 @@ cp -a ../gcc/jit/libgccjit*.h $FULLPATH/include/
 gzip -9 %{buildroot}/%{_infodir}/libgccjit.info
 
 pushd $FULLPATH
-echo '/* GNU ld script */
-%{oformat}
-INPUT ( %{?scl:%{_root_prefix}}%{!?scl:%{_prefix}}/%{_lib}/libgomp.so.1 )' > libgomp.so
-
 echo '/* GNU ld script
    Use the shared library, but some functions are only in
    the static library, so try that secondarily.  */
 %{oformat}
 INPUT ( %{?scl:%{_root_prefix}}%{!?scl:%{_prefix}}/%{_lib}/libstdc++.so.6 -lstdc++_nonshared )' > libstdc++.so
-rm -f libgfortran.so
-
-echo '/* GNU ld script */
-%{oformat}
-INPUT ( %{?scl:%{_prefix}}/%{_lib}/libgfortran.so.5 )' > libgfortran.so
 
 %if %{build_libquadmath}
 rm -f libquadmath.so
 echo '/* GNU ld script */
 %{oformat}
-%if 0%{!?scl:1}
 INPUT ( %{_prefix}/%{_lib}/libquadmath.so.0 )' > libquadmath.so
-%else
-INPUT ( %{_root_prefix}/%{_lib}/libquadmath.so.0 )' > libquadmath.so
-%endif
-%endif
-%if %{build_libitm}
-rm -f libitm.so
-echo '/* GNU ld script */
-%{oformat}
-INPUT ( %{?scl:%{_root_prefix}}%{!?scl:%{_prefix}}/%{_lib}/libitm.so.1 )' > libitm.so
-%endif
-%if %{build_libatomic}
-rm -f libatomic.so
-echo '/* GNU ld script */
-%{oformat}
-INPUT ( %{?scl:%{_root_prefix}}%{!?scl:%{_prefix}}/%{_lib}/libatomic.so.1 )' > libatomic.so
 %endif
+
 %if %{build_libasan}
 rm -f libasan.so
 echo '/* GNU ld script */
@@ -967,6 +952,14 @@ echo '/* GNU ld script */
 %{oformat}
 INPUT ( %{?scl:%{_prefix}}/%{_lib}/libtsan.so.2 )' > libtsan.so
 %endif
+ln -sf ../../../../%{_lib}/libgfortran.so.5.* libgfortran.so
+ln -sf ../../../../%{_lib}/libgomp.so.1.* libgomp.so
+%if %{build_libitm}
+ln -sf ../../../../%{_lib}/libitm.so.1.* libitm.so
+%endif
+%if %{build_libatomic}
+ln -sf ../../../../%{_lib}/libatomic.so.1.* libatomic.so
+%endif
 %if %{build_libubsan}
 rm -f libubsan.so
 echo '/* GNU ld script */
@@ -985,8 +978,9 @@ INPUT ( %{?scl:%{_prefix}}/%{_lib}/liblsan.so.0 )' > liblsan.so
 %endif
 mv -f %{buildroot}%{_prefix}/%{_lib}/libstdc++.*a $FULLLPATH/
 mv -f %{buildroot}%{_prefix}/%{_lib}/libstdc++fs.*a $FULLLPATH/
-mv -f %{buildroot}%{_prefix}/%{_lib}/libsupc++.*a .
-mv -f %{buildroot}%{_prefix}/%{_lib}/libgfortran.*a .
+mv -f %{buildroot}%{_prefix}/%{_lib}/libstdc++exp.*a $FULLLPATH/
+mv -f %{buildroot}%{_prefix}/%{_lib}/libsupc++.*a $FULLLPATH/
+mv -f %{buildroot}%{_prefix}/%{_lib}/libgfortran.*a $FULLLPATH/
 mv -f %{buildroot}%{_prefix}/%{_lib}/libgomp.*a .
 %if %{build_libquadmath}
 mv -f %{buildroot}%{_prefix}/%{_lib}/libquadmath.*a $FULLLPATH/
@@ -1018,20 +1012,16 @@ mv -f %{buildroot}%{_prefix}/%{_lib}/liblsan.*a $FULLPATH/
 mv -f %{buildroot}%{_prefix}/%{_lib}/liblsan_preinit.o $FULLPATH/
 %endif
 
+
 %ifarch sparcv9 ppc
 echo '/* GNU ld script
    Use the shared library, but some functions are only in
    the static library, so try that secondarily.  */
 %{oformat2}
 INPUT ( %{?scl:%{_root_prefix}}%{!?scl:%{_prefix}}/lib64/libstdc++.so.6 -lstdc++_nonshared )' > 64/libstdc++.so
-rm -f 64/libgfortran.so
-echo '/* GNU ld script */
+ln -sf ../`echo ../../../../lib/libgfortran.so.5.* | sed s~/lib/~/lib64/~` 64/libgfortran.so
+ln -sf ../`echo ../../../../lib/libgomp.so.1.* | sed s~/lib/~/lib64/~` 64/libgomp.so
 
-%{oformat2}
-INPUT ( %{_prefix}/lib64/libgfortran.so.5 )' > 64/libgfortran.so
-echo '/* GNU ld script */
-%{oformat2}
-INPUT ( %{?scl:%{_root_prefix}}%{!?scl:%{_prefix}}/lib64/libgomp.so.1 )' > 64/libgomp.so
 echo '/* GNU ld script */
 %{oformat2}
 INPUT ( %{_prefix}/lib64/libgccjit.so.0 )' > 64/libgccjit.so
@@ -1039,23 +1029,17 @@ INPUT ( %{_prefix}/lib64/libgccjit.so.0 )' > 64/libgccjit.so
 rm -f 64/libquadmath.so
 echo '/* GNU ld script */
 %{oformat2}
-%if 0%{!?scl:1}
 INPUT ( %{_prefix}/lib64/libquadmath.so.0 )' > 64/libquadmath.so
-%else
-INPUT ( %{_root_prefix}/lib64/libquadmath.so.0 )' > 64/libquadmath.so
-%endif
 %endif
 %if %{build_libitm}
-rm -f 64/libitm.so
-echo '/* GNU ld script */
-%{oformat2}
-INPUT ( %{?scl:%{_root_prefix}}%{!?scl:%{_prefix}}/lib64/libitm.so.1 )' > 64/libitm.so
+rm -f libitm.so
+echo 'INPUT ( %{_prefix}/lib/'`echo ../../../../lib/libitm.so.1.* | sed 's,^.*libi,libi,'`' )' > libitm.so
+echo 'INPUT ( %{_prefix}/lib64/'`echo ../../../../lib/libitm.so.1.* | sed 's,^.*libi,libi,'`' )' > 64/libitm.so
 %endif
 %if %{build_libatomic}
-rm -f 64/libatomic.so
-echo '/* GNU ld script */
-%{oformat2}
-INPUT ( %{?scl:%{_root_prefix}}%{!?scl:%{_prefix}}/lib64/libatomic.so.1 )' > 64/libatomic.so
+rm -f libatomic.so
+echo 'INPUT ( %{_prefix}/lib/'`echo ../../../../lib/libatomic.so.1.* | sed 's,^.*liba,liba,'`' )' > libatomic.so
+echo 'INPUT ( %{_prefix}/lib64/'`echo ../../../../lib/libatomic.so.1.* | sed 's,^.*liba,liba,'`' )' > 64/libatomic.so
 %endif
 %if %{build_libasan}
 rm -f 64/libasan.so
@@ -1069,18 +1053,22 @@ echo '/* GNU ld script */
 %{oformat2}
 INPUT ( %{?scl:%{_root_prefix}}%{!?scl:%{_prefix}}/lib64/libubsan.so.1 )' > 64/libubsan.so
 %endif
-mv -f %{buildroot}%{_prefix}/lib64/libsupc++.*a 64/
-mv -f %{buildroot}%{_prefix}/lib64/libgfortran.*a 64/
-mv -f %{buildroot}%{_prefix}/lib64/libgomp.*a 64/
+ln -sf lib32/libgfortran.a libgfortran.a
+ln -sf ../lib64/libgfortran.a 64/libgfortran.a
 %if %{build_libquadmath}
 mv -f %{buildroot}%{_prefix}/lib64/libquadmath.*a 64/
 %endif
+mv -f %{buildroot}%{_prefix}/lib64/libgomp.*a 64/
 ln -sf lib32/libstdc++.a libstdc++.a
 ln -sf ../lib64/libstdc++.a 64/libstdc++.a
 ln -sf lib32/libstdc++fs.a libstdc++fs.a
 ln -sf ../lib64/libstdc++fs.a 64/libstdc++fs.a
 ln -sf lib32/libstdc++_nonshared.a libstdc++_nonshared.a
 ln -sf ../lib64/libstdc++_nonshared.a 64/libstdc++_nonshared.a
+ln -sf lib32/libstdc++exp.a libstdc++exp.a
+ln -sf ../lib64/libstdc++exp.a 64/libstdc++exp.a
+ln -sf lib32/libsupc++.a libsupc++.a
+ln -sf ../lib64/libsupc++.a 64/libsupc++.a
 %if %{build_libquadmath}
 ln -sf lib32/libquadmath.a libquadmath.a
 ln -sf ../lib64/libquadmath.a 64/libquadmath.a
@@ -1104,6 +1092,8 @@ ln -sf lib32/libubsan.a libubsan.a
 ln -sf ../lib64/libubsan.a 64/libubsan.a
 %endif
 %endif
+
+
 %ifarch %{multilib_64_archs}
 mkdir -p 32
 echo '/* GNU ld script
@@ -1111,15 +1101,8 @@ echo '/* GNU ld script
    the static library, so try that secondarily.  */
 %{oformat2}
 INPUT ( %{?scl:%{_root_prefix}}%{!?scl:%{_prefix}}/lib/libstdc++.so.6 -lstdc++_nonshared )' > 32/libstdc++.so
-rm -f 32/libgfortran.so
-echo '/* GNU ld script */
-%{oformat2}
-INPUT ( %{_prefix}}/lib/libgfortran.so.5 )' > 32/libgfortran.so
-
-
-echo '/* GNU ld script */
-%{oformat2}
-INPUT ( %{?scl:%{_root_prefix}}%{!?scl:%{_prefix}}/lib/libgomp.so.1 )' > 32/libgomp.so
+ln -sf ../`echo ../../../../lib64/libgfortran.so.5.* | sed s~/../lib64/~/~` 32/libgfortran.so
+ln -sf ../`echo ../../../../lib64/libgomp.so.1.* | sed s~/../lib64/~/~` 32/libgomp.so
 
 echo '/* GNU ld script */
 %{oformat2}
@@ -1128,23 +1111,17 @@ INPUT ( %{_prefix}/lib/libgccjit.so.0 )' > 32/libgccjit.so
 rm -f 32/libquadmath.so
 echo '/* GNU ld script */
 %{oformat2}
-%if 0%{!?scl:1}
 INPUT ( %{_prefix}/lib/libquadmath.so.0 )' > 32/libquadmath.so
-%else
-INPUT ( %{_root_prefix}/lib/libquadmath.so.0 )' > 32/libquadmath.so
-%endif
 %endif
 %if %{build_libitm}
-rm -f 32/libitm.so
-echo '/* GNU ld script */
-%{oformat2}
-INPUT ( %{?scl:%{_root_prefix}}%{!?scl:%{_prefix}}/lib/libitm.so.1 )' > 32/libitm.so
+rm -f libitm.so
+echo 'INPUT ( %{_prefix}/lib64/'`echo ../../../../lib64/libitm.so.1.* | sed 's,^.*libi,libi,'`' )' > libitm.so
+echo 'INPUT ( %{_prefix}/lib/'`echo ../../../../lib64/libitm.so.1.* | sed 's,^.*libi,libi,'`' )' > 32/libitm.so
 %endif
 %if %{build_libatomic}
-rm -f 32/libatomic.so
-echo '/* GNU ld script */
-%{oformat2}
-INPUT ( %{?scl:%{_root_prefix}}%{!?scl:%{_prefix}}/lib/libatomic.so.1 )' > 32/libatomic.so
+rm -f libatomic.so
+echo 'INPUT ( %{_prefix}/lib64/'`echo ../../../../lib64/libatomic.so.1.* | sed 's,^.*liba,liba,'`' )' > libatomic.so
+echo 'INPUT ( %{_prefix}/lib/'`echo ../../../../lib64/libatomic.so.1.* | sed 's,^.*liba,liba,'`' )' > 32/libatomic.so
 %endif
 %if %{build_libasan}
 rm -f 32/libasan.so
@@ -1158,12 +1135,10 @@ echo '/* GNU ld script */
 %{oformat2}
 INPUT ( %{?scl:%{_root_prefix}}%{!?scl:%{_prefix}}/lib/libubsan.so.1 )' > 32/libubsan.so
 %endif
-mv -f %{buildroot}%{_prefix}/lib/libsupc++.*a 32/
-mv -f %{buildroot}%{_prefix}/lib/libgfortran.*a 32/
-mv -f %{buildroot}%{_prefix}/lib/libgomp.*a 32/
 %if %{build_libquadmath}
 mv -f %{buildroot}%{_prefix}/lib/libquadmath.*a 32/
 %endif
+mv -f %{buildroot}%{_prefix}/lib/libgomp.*a 32/
 %endif
 %ifarch sparc64 ppc64
 ln -sf ../lib32/libgfortran.a 32/libgfortran.a
@@ -1174,6 +1149,10 @@ ln -sf ../lib32/libstdc++fs.a 32/libstdc++fs.a
 ln -sf lib64/libstdc++fs.a libstdc++fs.a
 ln -sf ../lib32/libstdc++_nonshared.a 32/libstdc++_nonshared.a
 ln -sf lib64/libstdc++_nonshared.a libstdc++_nonshared.a
+ln -sf ../lib32/libstdc++exp.a 32/libstdc++exp.a
+ln -sf lib64/libstdc++exp.a libstdc++exp.a
+ln -sf ../lib32/libsupc++.a 32/libsupc++.a
+ln -sf lib64/libsupc++.a libsupc++.a
 %if %{build_libquadmath}
 ln -sf ../lib32/libquadmath.a 32/libquadmath.a
 ln -sf lib64/libquadmath.a libquadmath.a
@@ -1202,7 +1181,9 @@ mv -f lib64/libubsan.a libubsan.a
 ln -sf ../../../%{multilib_32_arch}-%{_vendor}-%{_target_os}/%{gcc_major}/libgfortran.a 32/libgfortran.a
 ln -sf ../../../%{multilib_32_arch}-%{_vendor}-%{_target_os}/%{gcc_major}/libstdc++.a 32/libstdc++.a
 ln -sf ../../../%{multilib_32_arch}-%{_vendor}-%{_target_os}/%{gcc_major}/libstdc++fs.a 32/libstdc++fs.a
-ln -sf ../../../%{multilib_32_arch}-%{_vendor}-%{_target_os}%{?_gnu}/%{gcc_major}/libstdc++_nonshared.a 32/libstdc++_nonshared.a
+ln -sf ../../../%{multilib_32_arch}-%{_vendor}-%{_target_os}/%{gcc_major}/libstdc++_nonshared.a 32/libstdc++_nonshared.a
+ln -sf ../../../%{multilib_32_arch}-%{_vendor}-%{_target_os}/%{gcc_major}/libstdc++exp.a 32/libstdc++exp.a
+ln -sf ../../../%{multilib_32_arch}-%{_vendor}-%{_target_os}/%{gcc_major}/libsupc++.a 32/libsupc++.a
 %if %{build_libquadmath}
 ln -sf ../../../%{multilib_32_arch}-%{_vendor}-%{_target_os}/%{gcc_major}/libquadmath.a 32/libquadmath.a
 %endif
@@ -1235,7 +1216,7 @@ for d in . $FULLLSUBDIR; do
 		    -o -name libtsan.a -o -name libubsan.a \
 		    -o -name liblsan.a \
 		    -o -name libstdc++_nonshared.a \
-		    -o -name libsupc++.a \
+		    -o -name libsupc++.a  -o -name libstdc++exp.a\
 		    -o -name libstdc++.a -o -name libcaf_single.a \
 		    -o -name libstdc++fs.a \) -a -type f`; do
     cp -a $f $RPM_BUILD_ROOT%{_prefix}/lib/debug%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/$d/
@@ -1261,28 +1242,13 @@ chrpath -d %{buildroot}%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/pl
 chmod 755 %{buildroot}%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/plugin/libcp1plugin.so*
 chrpath -d %{buildroot}%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/plugin/libcp1plugin.so*
 %if %{build_libquadmath}
-%if 0%{!?scl:1}
 chmod 755 %{buildroot}%{_prefix}/%{_lib}/libquadmath.so.0.*
 %endif
-%endif
 %if %{build_libitm}
 chmod 755 %{buildroot}%{_prefix}/%{_lib}/libitm.so.1.*
-%if 0%{?scl:1}
-mkdir -p %{buildroot}%{_root_prefix}/%{_lib}/
-mv %{buildroot}%{_prefix}/%{_lib}/libitm.so.1* %{buildroot}%{_root_prefix}/%{_lib}/
-mkdir -p %{buildroot}%{_root_infodir}
-
-mv %{buildroot}%{_infodir}/libitm.info* %{buildroot}%{_root_infodir}/
-
-%endif
 %endif
 %if %{build_libatomic}
 chmod 755 %{buildroot}%{_prefix}/%{_lib}/libatomic.so.1.*
-%if 0%{?scl:1}
-mkdir -p %{buildroot}%{_root_prefix}/%{_lib}/
-mv %{buildroot}%{_prefix}/%{_lib}/libatomic.so.1* %{buildroot}%{_root_prefix}/%{_lib}/
-mkdir -p %{buildroot}%{_root_infodir}
-%endif
 %endif
 %if %{build_libasan}
 chmod 755 %{buildroot}%{_prefix}/%{_lib}/libasan.so.8.*
@@ -1387,27 +1353,24 @@ cd ..
 
 # Remove binaries we will not be including, so that they don't end up in
 # gcc-debuginfo
-rm -f %{buildroot}%{_prefix}/%{_lib}/{libffi*,libiberty.a,libstdc++*,libgfortran*} || :
+rm -f %{buildroot}%{_prefix}/%{_lib}/{libffi*,libiberty.a,libstdc++.so*,libgfortran.so,libgcc_s.so} || :
 %if 0%{?scl:1}
-rm -f %{buildroot}%{_prefix}/%{_lib}/{libquadmath*,libitm*,libatomic*,libasan.so,libtsan.so,libubsan.so,liblsan.so}
-%else
-
-rm -f %{buildroot}%{_prefix}/%{_lib}/{libitm*,libatomic*}
-
+rm -f %{buildroot}%{_prefix}/%{_lib}/{libitm.so,libatomic.so,libasan.so,libtsan.so,libubsan.so,liblsan.so}
+%if %{build_libquadmath}
+rm -f %{buildroot}%{_prefix}/%{_lib}/{libquadmath.so}
 %endif
-rm -f %{buildroot}%{_prefix}/%{_lib}/libgomp*
-rm -f %{buildroot}/%{_lib}/libgcc_s*
+%if %{build_libhwasan}
+rm -f %{buildroot}%{_prefix}/%{_lib}/{libhwasan.so}
+%endif
+%endif
+rm -f %{buildroot}%{_prefix}/%{_lib}/libgomp.so
 rm -f $FULLEPATH/install-tools/{mkheaders,fixincl}
 rm -f %{buildroot}%{_prefix}/lib/{32,64}/libiberty.a
 rm -f %{buildroot}%{_prefix}/%{_lib}/libssp*
 rm -f %{buildroot}%{_prefix}/%{_lib}/libvtv* || :
 rm -f %{buildroot}/lib/cpp
-rm -f %{buildroot}/%{_lib}/libgcc_s*
 rm -f %{buildroot}%{_prefix}/bin/{gccbug,gnatgcc*}
 rm -f %{buildroot}%{_prefix}/bin/%{gcc_target_platform}-gfortran
-%if 0%{!?scl:1}
-rm -f %{buildroot}%{_prefix}/bin/{*c++*,cc,cpp}
-%endif
 rm -f %{buildroot}%{_prefix}/bin/%{_target_platform}-gfortran || :
 
 %ifarch %{multilib_64_archs}
@@ -1505,7 +1468,7 @@ end
 
 %ldconfig_scriptlets -n %{?_scl_prefix}libgccjit%{gcc_ver}
 
-%ldconfig_scriptlets -n %{?_scl_prefix}libquadmath%{gcc_ver}-devel
+%ldconfig_scriptlets -n %{?_scl_prefix}libquadmath%{gcc_ver}
 
 %ldconfig_scriptlets -n %{?_scl_prefix}libitm%{gcc_ver}
 
@@ -1693,6 +1656,12 @@ end
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/prfchiintrin.h
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/raointintrin.h
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/amxcomplexintrin.h
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/avx512bitalgvlintrin.h
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/avxvnniint16intrin.h
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/sha512intrin.h
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/sm3intrin.h
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/sm4intrin.h
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/usermsrintrin.h
 %endif
 %ifarch ia64
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/ia64intrin.h
@@ -1737,6 +1706,8 @@ end
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/arm_fp16.h
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/arm_bf16.h
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/arm_sve.h
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/arm_sme.h
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/arm_neon_sve_bridge.h
 %endif
 %ifarch sparc sparcv9 sparc64
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/visintrin.h
@@ -1753,22 +1724,22 @@ end
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/riscv_bitmanip.h
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/riscv_th_vector.h
 %endif
+%ifarch loongarch64
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/larchintrin.h
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/plugin/include/config/loongarch/loongarch-protos.h
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/plugin/include/config/loongarch/loongarch-opts.h
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/plugin/include/config/loongarch/loongarch-str.h
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/plugin/include/config/loongarch/loongarch-def.h
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/plugin/include/config/loongarch/loongarch-tune.h
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/plugin/include/config/loongarch/loongarch-driver.h
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/lsxintrin.h
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/lasxintrin.h
+%endif
 %if %{build_libasan}
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/sanitizer
 %endif
 %{_prefix}/libexec/gcc/%{gcc_target_platform}/%{gcc_major}/cc1
 %{_prefix}/libexec/gcc/%{gcc_target_platform}/%{gcc_major}/collect2
-%if 0%{?scl:1}
-%{_prefix}/libexec/gcc/%{gcc_target_platform}/%{gcc_major}/ar
-%{_prefix}/libexec/gcc/%{gcc_target_platform}/%{gcc_major}/as
-%{_prefix}/libexec/gcc/%{gcc_target_platform}/%{gcc_major}/ld
-%{_prefix}/libexec/gcc/%{gcc_target_platform}/%{gcc_major}/ld.bfd
-%{_prefix}/libexec/gcc/%{gcc_target_platform}/%{gcc_major}/ld.gold
-%{_prefix}/libexec/gcc/%{gcc_target_platform}/%{gcc_major}/nm
-%{_prefix}/libexec/gcc/%{gcc_target_platform}/%{gcc_major}/objcopy
-%{_prefix}/libexec/gcc/%{gcc_target_platform}/%{gcc_major}/ranlib
-%{_prefix}/libexec/gcc/%{gcc_target_platform}/%{gcc_major}/strip
-%endif
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/crt*.o
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libgcc.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libgcov.a
@@ -1829,8 +1800,6 @@ end
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/32/libgcc_s.so
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/32/libgomp.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/32/libgomp.so
-
-
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/32/libgccjit.so
 %if %{build_libquadmath}
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/32/libquadmath.a
@@ -1876,9 +1845,6 @@ end
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libubsan.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libubsan.so
 %endif
-%if %{build_libatomic}
-%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libatomic.so
-%endif
 %if %{build_libtsan}
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libtsan.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libtsan.so
@@ -1923,6 +1889,7 @@ end
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/64/libstdc++.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/64/libstdc++fs.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/64/libstdc++_nonshared.a
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/64/libstdc++exp.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/64/libsupc++.a
 %endif
 %ifarch %{multilib_64_archs}
@@ -1931,6 +1898,7 @@ end
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/32/libstdc++.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/32/libstdc++fs.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/32/libstdc++_nonshared.a
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/32/libstdc++exp.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/32/libsupc++.a
 %endif
 %ifarch sparcv9 ppc %{multilib_64_archs}
@@ -1941,6 +1909,8 @@ end
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libstdc++.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libstdc++fs.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libstdc++_nonshared.a
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libstdc++exp.a
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libsupc++.a
 %endif
 %doc rpm.doc/changelogs/gcc/cp/ChangeLog*
 
@@ -1956,17 +1926,20 @@ end
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/lib32/libstdc++.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/lib32/libstdc++fs.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/lib32/libstdc++_nonshared.a
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/lib32/libstdc++exp.a
 %endif
 %ifarch sparc64 ppc64
 %dir %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/lib64
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/lib64/libstdc++.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/lib64/libstdc++fs.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/lib64/libstdc++_nonshared.a
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/lib64/libstdc++exp.a
 %endif
 %ifnarch sparcv9 sparc64 ppc ppc64
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libstdc++.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libstdc++fs.a
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libstdc++_nonshared.a
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libstdc++exp.a
 %endif
 %ifnarch sparcv9 ppc %{multilib_64_archs}
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libstdc++.so
@@ -2033,6 +2006,7 @@ end
 %doc rpm.doc/gfortran/*
 
 %files -n %{?_scl_prefix}libgfortran%{gcc_ver}-devel
+%{_prefix}/%{_lib}/libgfortran.so.5*
 %dir %{_prefix}/lib/gcc
 %dir %{_prefix}/lib/gcc/%{gcc_target_platform}
 %dir %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}
@@ -2047,14 +2021,27 @@ end
 %ifnarch sparcv9 sparc64 ppc ppc64 ppc64p7
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libgfortran.a
 %endif
+%files -n %{?_scl_prefix}libgomp%{gcc_ver}
+%{_prefix}/%{_lib}/libgomp.so.1*
+%{_infodir}/libgomp.info*
+%doc rpm.doc/changelogs/libgomp/ChangeLog*
+
 %if %{build_libquadmath}
-%files -n %{?_scl_prefix}libquadmath%{gcc_ver}-devel
+%files -n %{?_scl_prefix}libquadmath%{gcc_ver}
+%{_prefix}/%{_lib}/libquadmath.so.0*
+%{_infodir}/libquadmath.info*
+%{!?_licensedir:%global license %%doc}
+%license rpm.doc/libquadmath/COPYING*
 %dir %{_prefix}/lib/gcc
 %dir %{_prefix}/lib/gcc/%{gcc_target_platform}
 %dir %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}
 %dir %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/quadmath.h
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include/quadmath_weak.h
+%ifnarch sparcv9 sparc64 ppc ppc64 ppc64p7
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libquadmath.so
+%endif
+%doc rpm.doc/libquadmath/ChangeLog*
 %ifarch sparcv9 ppc
 %dir %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/lib32
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/lib32/libquadmath.a
@@ -2065,17 +2052,24 @@ end
 %endif
 %ifnarch sparcv9 sparc64 ppc ppc64 ppc64p7
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libquadmath.a
-%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libquadmath.so
 %endif
-%dir %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}
-%doc rpm.doc/libquadmath/ChangeLog*
 %endif
 
 %if %{build_libitm}
-%files -n %{?_scl_prefix}libitm%{gcc_ver}-devel
+%files -n %{?_scl_prefix}libitm%{gcc_ver}
+%{_prefix}/%{_lib}/libitm.so.1*
+%{_infodir}/libitm.info*
 %dir %{_prefix}/lib/gcc
 %dir %{_prefix}/lib/gcc/%{gcc_target_platform}
 %dir %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}
+%dir %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/include
+#%%{_prefix}/lib/gcc/%%{gcc_target_platform}/%%{gcc_major}/include/itm.h
+#%%{_prefix}/lib/gcc/%%{gcc_target_platform}/%%{gcc_major}/include/itm_weak.h
+%ifnarch sparcv9 sparc64 ppc ppc64 ppc64p7
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libitm.so
+%endif
+%doc rpm.doc/libitm/ChangeLog*
+
 %ifarch sparcv9 ppc
 %dir %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/lib32
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/lib32/libitm.a
@@ -2085,14 +2079,20 @@ end
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/lib64/libitm.a
 %endif
 %ifnarch sparcv9 sparc64 ppc ppc64 ppc64p7
-%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libitm.so
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libitm.a
 %endif
-%doc rpm.doc/libitm/ChangeLog*
 %endif
 
 %if %{build_libatomic}
-%files -n %{?_scl_prefix}libatomic%{gcc_ver}-devel
+%files -n %{?_scl_prefix}libatomic%{gcc_ver}
+%{_prefix}/%{_lib}/libatomic.so.1*
+%ifarch sparcv9 ppc
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/64/libatomic.so
+%endif
+%ifarch %{multilib_64_archs}
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/32/libatomic.so
+%endif
+%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libatomic.so
 %dir %{_prefix}/lib/gcc
 %dir %{_prefix}/lib/gcc/%{gcc_target_platform}
 %dir %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}
@@ -2105,7 +2105,6 @@ end
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/lib64/libatomic.a
 %endif
 %ifnarch sparcv9 sparc64 ppc ppc64 ppc64p7
-%{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libatomic.so
 %{_prefix}/lib/gcc/%{gcc_target_platform}/%{gcc_major}/libatomic.a
 %endif
 %doc rpm.doc/changelogs/libatomic/ChangeLog*
@@ -2242,6 +2241,22 @@ end
 %doc rpm.doc/changelogs/libcc1/ChangeLog*
 
 %changelog
+* Mon Mar 3 2025 Peng Fan <fanpeng@loongson.cn> - 14.2.1-7
+- LoongArch: sync from upstream.
+
+* Wed Aug 28 2024 YunQiang Su <yunqiang@isrc.iscas.ac.cn> - 14.2.1-6
+- Fix build on RISC-V 64.
+
+* Wed Aug 28 2024 zhaoshujian <zhaoshujian@huawei.com> - 14.2.1-5
+- Change stdc++_nonshared_48 to stdc++_nonshared_80.
+
+* Tue Aug 27 2024 zhaoshujian <zhaoshujian@huawei.com> - 14.2.1-4
+- [bugfix] Change libsupc++.a, libstdc++exp.a package path
+
+* Sat Aug 24 2024 zhaoshujian <zhaoshujian@huawei.com> - 14.2.1-3
+- [bugfix] Change libgomp, libfortran, libgcc_s, libitm, libatomic package path
+- Add gcc-toolset-14 Readme
+
 * Thu Aug 22 2024 Hu, Lin <lin1.hu@intel.com> - 14.2.1-2
 - [Backport] Backport fix prefetchi from gcc-14.3.0