54 lines
1.5 KiB
Diff
54 lines
1.5 KiB
Diff
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From 89dfb9ad8687f9b31be5925b2d106b6ec13cc628 Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Sat, 9 Dec 2023 18:02:35 +0800
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Subject: [PATCH 072/188] LoongArch: Add alslsi3_extend
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Following the instruction cost fix, we are generating
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alsl.w $a0, $a0, $a0, 4
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instead of
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li.w $t0, 17
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mul.w $a0, $t0
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for "x * 4", because alsl.w is 4 times faster than mul.w. But we didn't
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have a sign-extending pattern for alsl.w, causing an extra slli.w
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instruction generated to sign-extend $a0. Add the pattern to remove the
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redundant extension.
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gcc/ChangeLog:
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* config/loongarch/loongarch.md (alslsi3_extend): New
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define_insn.
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---
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gcc/config/loongarch/loongarch.md | 12 ++++++++++++
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1 file changed, 12 insertions(+)
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diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
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index 222f1ae83..23368008e 100644
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--- a/gcc/config/loongarch/loongarch.md
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+++ b/gcc/config/loongarch/loongarch.md
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@@ -2874,6 +2874,18 @@
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[(set_attr "type" "arith")
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(set_attr "mode" "<MODE>")])
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+(define_insn "alslsi3_extend"
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+ [(set (match_operand:DI 0 "register_operand" "=r")
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+ (sign_extend:DI
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+ (plus:SI
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+ (ashift:SI (match_operand:SI 1 "register_operand" "r")
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+ (match_operand 2 "const_immalsl_operand" ""))
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+ (match_operand:SI 3 "register_operand" "r"))))]
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+ ""
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+ "alsl.w\t%0,%1,%3,%2"
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+ [(set_attr "type" "arith")
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+ (set_attr "mode" "SI")])
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+
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;; Reverse the order of bytes of operand 1 and store the result in operand 0.
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--
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2.43.0
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