117 lines
4.8 KiB
Diff
117 lines
4.8 KiB
Diff
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From b23a89e835962ae7d89e5c6f87a69c021097d715 Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Mon, 30 Oct 2023 20:24:58 +0800
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Subject: [PATCH 025/188] LoongArch: Optimize single-used address with
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-mexplicit-relocs=auto for fld/fst
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fld and fst have same address mode as ld.w and st.w, so the same
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optimization as r14-4851 should be applied for them too.
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gcc/ChangeLog:
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* config/loongarch/loongarch.md (LD_AT_LEAST_32_BIT): New mode
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iterator.
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(ST_ANY): New mode iterator.
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(define_peephole2): Use LD_AT_LEAST_32_BIT instead of GPR and
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ST_ANY instead of QHWD for applicable patterns.
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---
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gcc/config/loongarch/loongarch.md | 38 +++++++++++++++++++------------
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1 file changed, 24 insertions(+), 14 deletions(-)
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diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
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index 80487488d..ed86c95bd 100644
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--- a/gcc/config/loongarch/loongarch.md
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+++ b/gcc/config/loongarch/loongarch.md
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@@ -400,6 +400,14 @@
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(DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
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(TF "TARGET_64BIT && TARGET_DOUBLE_FLOAT")])
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+;; A mode for anything with 32 bits or more, and able to be loaded with
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+;; the same addressing mode as ld.w.
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+(define_mode_iterator LD_AT_LEAST_32_BIT [GPR ANYF])
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+
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+;; A mode for anything able to be stored with the same addressing mode as
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+;; st.w.
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+(define_mode_iterator ST_ANY [QHWD ANYF])
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+
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;; In GPR templates, a string like "mul.<d>" will expand to "mul.w" in the
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;; 32-bit version and "mul.d" in the 64-bit version.
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(define_mode_attr d [(SI "w") (DI "d")])
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@@ -3785,13 +3793,14 @@
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(define_peephole2
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[(set (match_operand:P 0 "register_operand")
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(match_operand:P 1 "symbolic_pcrel_operand"))
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- (set (match_operand:GPR 2 "register_operand")
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- (mem:GPR (match_dup 0)))]
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+ (set (match_operand:LD_AT_LEAST_32_BIT 2 "register_operand")
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+ (mem:LD_AT_LEAST_32_BIT (match_dup 0)))]
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"la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
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&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
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&& (peep2_reg_dead_p (2, operands[0]) \
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|| REGNO (operands[0]) == REGNO (operands[2]))"
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- [(set (match_dup 2) (mem:GPR (lo_sum:P (match_dup 0) (match_dup 1))))]
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+ [(set (match_dup 2)
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+ (mem:LD_AT_LEAST_32_BIT (lo_sum:P (match_dup 0) (match_dup 1))))]
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{
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emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
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})
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@@ -3799,14 +3808,15 @@
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(define_peephole2
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[(set (match_operand:P 0 "register_operand")
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(match_operand:P 1 "symbolic_pcrel_operand"))
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- (set (match_operand:GPR 2 "register_operand")
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- (mem:GPR (plus (match_dup 0)
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- (match_operand 3 "const_int_operand"))))]
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+ (set (match_operand:LD_AT_LEAST_32_BIT 2 "register_operand")
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+ (mem:LD_AT_LEAST_32_BIT (plus (match_dup 0)
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+ (match_operand 3 "const_int_operand"))))]
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"la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
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&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
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&& (peep2_reg_dead_p (2, operands[0]) \
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|| REGNO (operands[0]) == REGNO (operands[2]))"
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- [(set (match_dup 2) (mem:GPR (lo_sum:P (match_dup 0) (match_dup 1))))]
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+ [(set (match_dup 2)
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+ (mem:LD_AT_LEAST_32_BIT (lo_sum:P (match_dup 0) (match_dup 1))))]
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{
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operands[1] = plus_constant (Pmode, operands[1], INTVAL (operands[3]));
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emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
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@@ -3850,13 +3860,13 @@
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(define_peephole2
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[(set (match_operand:P 0 "register_operand")
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(match_operand:P 1 "symbolic_pcrel_operand"))
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- (set (mem:QHWD (match_dup 0))
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- (match_operand:QHWD 2 "register_operand"))]
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+ (set (mem:ST_ANY (match_dup 0))
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+ (match_operand:ST_ANY 2 "register_operand"))]
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"la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
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&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
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&& (peep2_reg_dead_p (2, operands[0])) \
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&& REGNO (operands[0]) != REGNO (operands[2])"
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- [(set (mem:QHWD (lo_sum:P (match_dup 0) (match_dup 1))) (match_dup 2))]
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+ [(set (mem:ST_ANY (lo_sum:P (match_dup 0) (match_dup 1))) (match_dup 2))]
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{
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emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
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})
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@@ -3864,14 +3874,14 @@
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(define_peephole2
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[(set (match_operand:P 0 "register_operand")
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(match_operand:P 1 "symbolic_pcrel_operand"))
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- (set (mem:QHWD (plus (match_dup 0)
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- (match_operand 3 "const_int_operand")))
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- (match_operand:QHWD 2 "register_operand"))]
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+ (set (mem:ST_ANY (plus (match_dup 0)
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+ (match_operand 3 "const_int_operand")))
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+ (match_operand:ST_ANY 2 "register_operand"))]
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"la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
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&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
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&& (peep2_reg_dead_p (2, operands[0])) \
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&& REGNO (operands[0]) != REGNO (operands[2])"
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- [(set (mem:QHWD (lo_sum:P (match_dup 0) (match_dup 1))) (match_dup 2))]
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+ [(set (mem:ST_ANY (lo_sum:P (match_dup 0) (match_dup 1))) (match_dup 2))]
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{
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operands[1] = plus_constant (Pmode, operands[1], INTVAL (operands[3]));
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emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
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--
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2.43.0
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