229 lines
7.6 KiB
Diff
229 lines
7.6 KiB
Diff
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From 9b19eb071fe3826aa61567b927fc95a37f6560f7 Mon Sep 17 00:00:00 2001
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From: Lulu Cheng <chenglulu@loongson.cn>
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Date: Fri, 8 Dec 2023 10:16:48 +0800
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Subject: [PATCH 108/188] LoongArch: Optimized some of the symbolic expansion
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instructions generated during bitwise operations.
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There are two mode iterators defined in the loongarch.md:
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(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
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and
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(define_mode_iterator X [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")])
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Replace the mode in the bit arithmetic from GPR to X.
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Since the bitwise operation instruction does not distinguish between 64-bit,
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32-bit, etc., it is necessary to perform symbolic expansion if the bitwise
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operation is less than 64 bits.
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The original definition would have generated a lot of redundant symbolic
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extension instructions. This problem is optimized with reference to the
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implementation of RISCV.
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Add this patch spec2017 500.perlbench performance improvement by 1.8%
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gcc/ChangeLog:
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* config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
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(*nor<mode>3): Likewise.
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(nor<mode>3): Likewise.
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(*negsi2_extended): New template.
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(*<optab>si3_internal): Likewise.
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(*one_cmplsi2_internal): Likewise.
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(*norsi3_internal): Likewise.
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(*<optab>nsi_internal): Likewise.
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(bytepick_w_<bytepick_imm>_extend): Modify this template according to the
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modified bit operation to make the optimization work.
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gcc/testsuite/ChangeLog:
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* gcc.target/loongarch/sign-extend-bitwise.c: New test.
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---
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gcc/config/loongarch/loongarch.md | 93 ++++++++++++++-----
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.../loongarch/sign-extend-bitwise.c | 21 +++++
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2 files changed, 90 insertions(+), 24 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c
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diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
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index 23653a2b0..6ebf33cbe 100644
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--- a/gcc/config/loongarch/loongarch.md
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+++ b/gcc/config/loongarch/loongarch.md
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@@ -736,7 +736,7 @@
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(define_insn "sub<mode>3"
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[(set (match_operand:GPR 0 "register_operand" "=r")
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- (minus:GPR (match_operand:GPR 1 "register_operand" "rJ")
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+ (minus:GPR (match_operand:GPR 1 "register_operand" "r")
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(match_operand:GPR 2 "register_operand" "r")))]
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""
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"sub.<d>\t%0,%z1,%2"
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@@ -1412,13 +1412,13 @@
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[(set_attr "alu_type" "sub")
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(set_attr "mode" "<MODE>")])
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-(define_insn "one_cmpl<mode>2"
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- [(set (match_operand:GPR 0 "register_operand" "=r")
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- (not:GPR (match_operand:GPR 1 "register_operand" "r")))]
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- ""
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- "nor\t%0,%.,%1"
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- [(set_attr "alu_type" "not")
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- (set_attr "mode" "<MODE>")])
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+(define_insn "*negsi2_extended"
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+ [(set (match_operand:DI 0 "register_operand" "=r")
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+ (sign_extend:DI (neg:SI (match_operand:SI 1 "register_operand" "r"))))]
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+ "TARGET_64BIT"
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+ "sub.w\t%0,%.,%1"
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+ [(set_attr "alu_type" "sub")
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+ (set_attr "mode" "SI")])
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(define_insn "neg<mode>2"
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[(set (match_operand:ANYF 0 "register_operand" "=f")
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@@ -1438,14 +1438,39 @@
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;;
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(define_insn "<optab><mode>3"
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- [(set (match_operand:GPR 0 "register_operand" "=r,r")
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- (any_bitwise:GPR (match_operand:GPR 1 "register_operand" "%r,r")
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- (match_operand:GPR 2 "uns_arith_operand" "r,K")))]
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+ [(set (match_operand:X 0 "register_operand" "=r,r")
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+ (any_bitwise:X (match_operand:X 1 "register_operand" "%r,r")
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+ (match_operand:X 2 "uns_arith_operand" "r,K")))]
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""
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"<insn>%i2\t%0,%1,%2"
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[(set_attr "type" "logical")
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(set_attr "mode" "<MODE>")])
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+(define_insn "*<optab>si3_internal"
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+ [(set (match_operand:SI 0 "register_operand" "=r,r")
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+ (any_bitwise:SI (match_operand:SI 1 "register_operand" "%r,r")
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+ (match_operand:SI 2 "uns_arith_operand" " r,K")))]
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+ "TARGET_64BIT"
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+ "<insn>%i2\t%0,%1,%2"
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+ [(set_attr "type" "logical")
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+ (set_attr "mode" "SI")])
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+
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+(define_insn "one_cmpl<mode>2"
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+ [(set (match_operand:X 0 "register_operand" "=r")
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+ (not:X (match_operand:X 1 "register_operand" "r")))]
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+ ""
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+ "nor\t%0,%.,%1"
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+ [(set_attr "alu_type" "not")
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+ (set_attr "mode" "<MODE>")])
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+
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+(define_insn "*one_cmplsi2_internal"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ (not:SI (match_operand:SI 1 "register_operand" " r")))]
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+ "TARGET_64BIT"
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+ "nor\t%0,%.,%1"
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+ [(set_attr "type" "logical")
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+ (set_attr "mode" "SI")])
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+
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(define_insn "and<mode>3_extended"
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[(set (match_operand:GPR 0 "register_operand" "=r")
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(and:GPR (match_operand:GPR 1 "nonimmediate_operand" "r")
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@@ -1561,25 +1586,43 @@
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[(set_attr "type" "logical")
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(set_attr "mode" "HI")])
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-(define_insn "*nor<mode>3"
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- [(set (match_operand:GPR 0 "register_operand" "=r")
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- (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "%r"))
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- (not:GPR (match_operand:GPR 2 "register_operand" "r"))))]
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+(define_insn "nor<mode>3"
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+ [(set (match_operand:X 0 "register_operand" "=r")
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+ (and:X (not:X (match_operand:X 1 "register_operand" "%r"))
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+ (not:X (match_operand:X 2 "register_operand" "r"))))]
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""
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"nor\t%0,%1,%2"
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[(set_attr "type" "logical")
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(set_attr "mode" "<MODE>")])
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+(define_insn "*norsi3_internal"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ (and:SI (not:SI (match_operand:SI 1 "register_operand" "%r"))
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+ (not:SI (match_operand:SI 2 "register_operand" "r"))))]
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+ "TARGET_64BIT"
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+ "nor\t%0,%1,%2"
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+ [(set_attr "type" "logical")
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+ (set_attr "mode" "SI")])
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+
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(define_insn "<optab>n<mode>"
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- [(set (match_operand:GPR 0 "register_operand" "=r")
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- (neg_bitwise:GPR
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- (not:GPR (match_operand:GPR 1 "register_operand" "r"))
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- (match_operand:GPR 2 "register_operand" "r")))]
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+ [(set (match_operand:X 0 "register_operand" "=r")
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+ (neg_bitwise:X
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+ (not:X (match_operand:X 1 "register_operand" "r"))
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+ (match_operand:X 2 "register_operand" "r")))]
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""
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"<insn>n\t%0,%2,%1"
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[(set_attr "type" "logical")
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(set_attr "mode" "<MODE>")])
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+(define_insn "*<optab>nsi_internal"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ (neg_bitwise:SI
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+ (not:SI (match_operand:SI 1 "register_operand" "r"))
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+ (match_operand:SI 2 "register_operand" "r")))]
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+ "TARGET_64BIT"
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+ "<insn>n\t%0,%2,%1"
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+ [(set_attr "type" "logical")
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+ (set_attr "mode" "SI")])
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;;
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;; ....................
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@@ -3167,7 +3210,6 @@
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(label_ref (match_operand 1))
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(pc)))])
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-
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;;
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;; ....................
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@@ -3967,10 +4009,13 @@
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(define_insn "bytepick_w_<bytepick_imm>_extend"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI
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- (ior:SI (lshiftrt (match_operand:SI 1 "register_operand" "r")
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- (const_int <bytepick_w_lshiftrt_amount>))
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- (ashift (match_operand:SI 2 "register_operand" "r")
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- (const_int bytepick_w_ashift_amount)))))]
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+ (subreg:SI
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+ (ior:DI (subreg:DI (lshiftrt
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+ (match_operand:SI 1 "register_operand" "r")
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+ (const_int <bytepick_w_lshiftrt_amount>)) 0)
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+ (subreg:DI (ashift
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+ (match_operand:SI 2 "register_operand" "r")
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+ (const_int bytepick_w_ashift_amount)) 0)) 0)))]
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"TARGET_64BIT"
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"bytepick.w\t%0,%1,%2,<bytepick_imm>"
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[(set_attr "mode" "SI")])
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diff --git a/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c b/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c
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new file mode 100644
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index 000000000..5753ef69d
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/sign-extend-bitwise.c
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@@ -0,0 +1,21 @@
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+/* { dg-do compile } */
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+/* { dg-options "-mabi=lp64d -O2" } */
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+/* { dg-final { scan-assembler-not "slli.w\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,0" } } */
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+
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+struct pmop
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+{
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+ unsigned int op_pmflags;
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+ unsigned int op_pmpermflags;
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+};
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+unsigned int PL_hints;
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+
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+struct pmop *pmop;
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+void
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+Perl_newPMOP (int type, int flags)
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+{
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+ if (PL_hints & 0x00100000)
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+ pmop->op_pmpermflags |= 0x0001;
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+ if (PL_hints & 0x00000004)
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+ pmop->op_pmpermflags |= 0x0800;
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+ pmop->op_pmflags = pmop->op_pmpermflags;
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+}
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--
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2.43.0
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