106 lines
3.6 KiB
Diff
106 lines
3.6 KiB
Diff
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From aa947bf395b5722a23f2edd9d6302e220473d900 Mon Sep 17 00:00:00 2001
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From: Chenghui Pan <panchenghui@loongson.cn>
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Date: Wed, 11 Oct 2023 16:41:25 +0800
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Subject: [PATCH 009/188] LoongArch: Fix vec_initv32qiv16qi template to avoid
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ICE.
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Following test code triggers unrecognized insn ICE on LoongArch target
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with "-O3 -mlasx":
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void
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foo (unsigned char *dst, unsigned char *src)
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{
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for (int y = 0; y < 16; y++)
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{
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for (int x = 0; x < 16; x++)
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dst[x] = src[x] + 1;
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dst += 32;
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src += 32;
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}
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}
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ICE info:
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./test.c: In function ‘foo’:
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./test.c:8:1: error: unrecognizable insn:
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8 | }
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| ^
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(insn 15 14 16 4 (set (reg:V32QI 185 [ vect__24.7 ])
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(vec_concat:V32QI (reg:V16QI 186)
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(const_vector:V16QI [
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(const_int 0 [0]) repeated x16
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]))) "./test.c":4:19 -1
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(nil))
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during RTL pass: vregs
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./test.c:8:1: internal compiler error: in extract_insn, at recog.cc:2791
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0x12028023b _fatal_insn(char const*, rtx_def const*, char const*, int, char const*)
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/home/panchenghui/upstream/gcc/gcc/rtl-error.cc:108
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0x12028026f _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
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/home/panchenghui/upstream/gcc/gcc/rtl-error.cc:116
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0x120a03c5b extract_insn(rtx_insn*)
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/home/panchenghui/upstream/gcc/gcc/recog.cc:2791
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0x12067ff73 instantiate_virtual_regs_in_insn
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/home/panchenghui/upstream/gcc/gcc/function.cc:1610
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0x12067ff73 instantiate_virtual_regs
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/home/panchenghui/upstream/gcc/gcc/function.cc:1983
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0x12067ff73 execute
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/home/panchenghui/upstream/gcc/gcc/function.cc:2030
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This RTL is generated inside loongarch_expand_vector_group_init function (related
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to vec_initv32qiv16qi template). Original impl doesn't ensure all vec_concat arguments
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are register type. This patch adds force_reg() to the vec_concat argument generation.
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gcc/ChangeLog:
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* config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
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fix impl related to vec_initv32qiv16qi template to avoid ICE.
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gcc/testsuite/ChangeLog:
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* gcc.target/loongarch/vector/lasx/lasx-vec-init-1.c: New test.
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---
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gcc/config/loongarch/loongarch.cc | 3 ++-
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.../loongarch/vector/lasx/lasx-vec-init-1.c | 14 ++++++++++++++
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2 files changed, 16 insertions(+), 1 deletion(-)
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create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-init-1.c
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diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
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index 760b12268..9a629a999 100644
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--- a/gcc/config/loongarch/loongarch.cc
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+++ b/gcc/config/loongarch/loongarch.cc
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@@ -10188,7 +10188,8 @@ loongarch_gen_const_int_vector_shuffle (machine_mode mode, int val)
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void
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loongarch_expand_vector_group_init (rtx target, rtx vals)
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{
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- rtx ops[2] = { XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1) };
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+ rtx ops[2] = { force_reg (E_V16QImode, XVECEXP (vals, 0, 0)),
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+ force_reg (E_V16QImode, XVECEXP (vals, 0, 1)) };
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emit_insn (gen_rtx_SET (target, gen_rtx_VEC_CONCAT (E_V32QImode, ops[0],
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ops[1])));
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}
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diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-init-1.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-init-1.c
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new file mode 100644
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index 000000000..28be32982
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-init-1.c
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@@ -0,0 +1,14 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O3" } */
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+
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+void
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+foo (unsigned char *dst, unsigned char *src)
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+{
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+ for (int y = 0; y < 16; y++)
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+ {
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+ for (int x = 0; x < 16; x++)
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+ dst[x] = src[x] + 1;
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+ dst += 32;
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+ src += 32;
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+ }
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+}
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--
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2.43.0
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