209 lines
7.6 KiB
Diff
209 lines
7.6 KiB
Diff
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From 416bdd180a6c0dab4736a6da26de245cb0487c0e Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Fri, 25 Oct 2024 02:13:53 +0000
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Subject: [PATCH 039/188] LoongArch: Add fine-grained control for LAM_BH and
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LAMCAS
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gcc/ChangeLog:
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* config/loongarch/genopts/isa-evolution.in: (lam-bh, lamcas):
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Add.
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* config/loongarch/loongarch-str.h: Regenerate.
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* config/loongarch/loongarch.opt: Regenerate.
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* config/loongarch/loongarch-cpucfg-map.h: Regenerate.
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* config/loongarch/loongarch-cpu.cc
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(ISA_BASE_LA64V110_FEATURES): Include OPTION_MASK_ISA_LAM_BH
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and OPTION_MASK_ISA_LAMCAS.
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* config/loongarch/sync.md (atomic_add<mode:SHORT>): Use
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TARGET_LAM_BH instead of ISA_BASE_IS_LA64V110. Remove empty
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lines from assembly output.
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(atomic_exchange<mode>_short): Likewise.
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(atomic_exchange<mode:SHORT>): Likewise.
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(atomic_fetch_add<mode>_short): Likewise.
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(atomic_fetch_add<mode:SHORT>): Likewise.
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(atomic_cas_value_strong<mode>_amcas): Use TARGET_LAMCAS instead
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of ISA_BASE_IS_LA64V110.
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(atomic_compare_and_swap<mode>): Likewise.
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(atomic_compare_and_swap<mode:GPR>): Likewise.
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(atomic_compare_and_swap<mode:SHORT>): Likewise.
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* config/loongarch/loongarch.cc (loongarch_asm_code_end): Dump
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status if -mlam-bh and -mlamcas if -fverbose-asm.
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---
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gcc/config/loongarch/genopts/isa-evolution.in | 2 ++
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gcc/config/loongarch/loongarch-cpu.cc | 3 ++-
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gcc/config/loongarch/loongarch-cpucfg-map.h | 2 ++
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gcc/config/loongarch/loongarch-str.h | 2 ++
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gcc/config/loongarch/loongarch.cc | 2 ++
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gcc/config/loongarch/loongarch.opt | 8 ++++++++
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gcc/config/loongarch/sync.md | 18 +++++++++---------
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7 files changed, 27 insertions(+), 10 deletions(-)
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diff --git a/gcc/config/loongarch/genopts/isa-evolution.in b/gcc/config/loongarch/genopts/isa-evolution.in
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index e58f0d6a1..a6bc3f87f 100644
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--- a/gcc/config/loongarch/genopts/isa-evolution.in
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+++ b/gcc/config/loongarch/genopts/isa-evolution.in
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@@ -1,2 +1,4 @@
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2 26 div32 Support div.w[u] and mod.w[u] instructions with inputs not sign-extended.
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+2 27 lam-bh Support am{swap/add}[_db].{b/h} instructions.
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+2 28 lamcas Support amcas[_db].{b/h/w/d} instructions.
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3 23 ld-seq-sa Do not need load-load barriers (dbar 0x700).
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diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc
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index 76d66fa55..bbce82c9c 100644
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--- a/gcc/config/loongarch/loongarch-cpu.cc
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+++ b/gcc/config/loongarch/loongarch-cpu.cc
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@@ -38,7 +38,8 @@ along with GCC; see the file COPYING3. If not see
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initializers! */
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#define ISA_BASE_LA64V110_FEATURES \
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- (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA)
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+ (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA \
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+ | OPTION_MASK_ISA_LAM_BH | OPTION_MASK_ISA_LAMCAS)
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int64_t loongarch_isa_base_features[N_ISA_BASE_TYPES] = {
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/* [ISA_BASE_LA64V100] = */ 0,
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diff --git a/gcc/config/loongarch/loongarch-cpucfg-map.h b/gcc/config/loongarch/loongarch-cpucfg-map.h
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index 0c078c397..02ff16712 100644
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--- a/gcc/config/loongarch/loongarch-cpucfg-map.h
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+++ b/gcc/config/loongarch/loongarch-cpucfg-map.h
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@@ -30,6 +30,8 @@ static constexpr struct {
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HOST_WIDE_INT isa_evolution_bit;
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} cpucfg_map[] = {
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{ 2, 1u << 26, OPTION_MASK_ISA_DIV32 },
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+ { 2, 1u << 27, OPTION_MASK_ISA_LAM_BH },
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+ { 2, 1u << 28, OPTION_MASK_ISA_LAMCAS },
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{ 3, 1u << 23, OPTION_MASK_ISA_LD_SEQ_SA },
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};
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diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
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index cd9dbb41b..0fee9abe5 100644
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--- a/gcc/config/loongarch/loongarch-str.h
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+++ b/gcc/config/loongarch/loongarch-str.h
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@@ -70,5 +70,7 @@ along with GCC; see the file COPYING3. If not see
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#define STR_EXPLICIT_RELOCS_ALWAYS "always"
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#define OPTSTR_DIV32 "div32"
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+#define OPTSTR_LAM_BH "lam-bh"
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+#define OPTSTR_LAMCAS "lamcas"
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#define OPTSTR_LD_SEQ_SA "ld-seq-sa"
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#endif /* LOONGARCH_STR_H */
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diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
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index c86b787c4..33d23a731 100644
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--- a/gcc/config/loongarch/loongarch.cc
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+++ b/gcc/config/loongarch/loongarch.cc
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@@ -11448,6 +11448,8 @@ loongarch_asm_code_end (void)
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fprintf (asm_out_file, "%s Base ISA: %s\n", ASM_COMMENT_START,
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loongarch_isa_base_strings [la_target.isa.base]);
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DUMP_FEATURE (TARGET_DIV32);
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+ DUMP_FEATURE (TARGET_LAM_BH);
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+ DUMP_FEATURE (TARGET_LAMCAS);
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DUMP_FEATURE (TARGET_LD_SEQ_SA);
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}
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diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
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index 5251f705d..ea0d5bb4e 100644
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--- a/gcc/config/loongarch/loongarch.opt
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+++ b/gcc/config/loongarch/loongarch.opt
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@@ -267,6 +267,14 @@ mdiv32
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Target Mask(ISA_DIV32) Var(isa_evolution)
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Support div.w[u] and mod.w[u] instructions with inputs not sign-extended.
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+mlam-bh
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+Target Mask(ISA_LAM_BH) Var(isa_evolution)
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+Support am{swap/add}[_db].{b/h} instructions.
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+
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+mlamcas
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+Target Mask(ISA_LAMCAS) Var(isa_evolution)
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+Support amcas[_db].{b/h/w/d} instructions.
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+
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mld-seq-sa
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Target Mask(ISA_LD_SEQ_SA) Var(isa_evolution)
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Do not need load-load barriers (dbar 0x700).
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diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md
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index 65443c899..a678e7131 100644
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--- a/gcc/config/loongarch/sync.md
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+++ b/gcc/config/loongarch/sync.md
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@@ -124,7 +124,7 @@
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return "ld.<size>\t%0,%1\\n\\t"
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"dbar\t0x14";
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case MEMMODEL_RELAXED:
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- return TARGET_LD_SEQ_SA ? "ld.<size>\t%0,%1\\n\\t"
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+ return TARGET_LD_SEQ_SA ? "ld.<size>\t%0,%1"
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: "ld.<size>\t%0,%1\\n\\t"
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"dbar\t0x700";
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@@ -193,7 +193,7 @@
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(match_operand:SHORT 1 "reg_or_0_operand" "rJ"))
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(match_operand:SI 2 "const_int_operand")] ;; model
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UNSPEC_SYNC_OLD_OP))]
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- "ISA_BASE_IS_LA64V110"
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+ "TARGET_LAM_BH"
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"amadd%A2.<amo>\t$zero,%z1,%0"
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[(set (attr "length") (const_int 4))])
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@@ -230,7 +230,7 @@
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UNSPEC_SYNC_EXCHANGE))
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(set (match_dup 1)
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(match_operand:SHORT 2 "register_operand" "r"))]
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- "ISA_BASE_IS_LA64V110"
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+ "TARGET_LAM_BH"
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"amswap%A3.<amo>\t%0,%z2,%1"
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[(set (attr "length") (const_int 4))])
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@@ -266,7 +266,7 @@
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(match_operand:QHWD 3 "reg_or_0_operand" "rJ")
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(match_operand:SI 4 "const_int_operand")] ;; mod_s
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UNSPEC_COMPARE_AND_SWAP))]
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- "ISA_BASE_IS_LA64V110"
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+ "TARGET_LAMCAS"
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"ori\t%0,%z2,0\n\tamcas%A4.<amo>\t%0,%z3,%1"
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[(set (attr "length") (const_int 8))])
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@@ -296,7 +296,7 @@
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operands[6] = mod_s;
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- if (ISA_BASE_IS_LA64V110)
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+ if (TARGET_LAMCAS)
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emit_insn (gen_atomic_cas_value_strong<mode>_amcas (operands[1], operands[2],
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operands[3], operands[4],
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operands[6]));
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@@ -422,7 +422,7 @@
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operands[6] = mod_s;
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- if (ISA_BASE_IS_LA64V110)
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+ if (TARGET_LAMCAS)
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emit_insn (gen_atomic_cas_value_strong<mode>_amcas (operands[1], operands[2],
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operands[3], operands[4],
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operands[6]));
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@@ -642,7 +642,7 @@
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(match_operand:SHORT 2 "register_operand"))]
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""
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{
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- if (ISA_BASE_IS_LA64V110)
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+ if (TARGET_LAM_BH)
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emit_insn (gen_atomic_exchange<mode>_short (operands[0], operands[1], operands[2], operands[3]));
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else
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{
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@@ -663,7 +663,7 @@
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(match_operand:SHORT 2 "reg_or_0_operand" "rJ"))
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(match_operand:SI 3 "const_int_operand")] ;; model
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UNSPEC_SYNC_OLD_OP))]
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- "ISA_BASE_IS_LA64V110"
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+ "TARGET_LAM_BH"
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"amadd%A3.<amo>\t%0,%z2,%1"
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[(set (attr "length") (const_int 4))])
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@@ -678,7 +678,7 @@
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UNSPEC_SYNC_OLD_OP))]
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""
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{
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- if (ISA_BASE_IS_LA64V110)
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+ if (TARGET_LAM_BH)
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emit_insn (gen_atomic_fetch_add<mode>_short (operands[0], operands[1],
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operands[2], operands[3]));
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else
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--
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2.43.0
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