225 lines
6.0 KiB
Diff
225 lines
6.0 KiB
Diff
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From 54bf8fc616af5cdb9e4c787a2dfb2c516c8e425a Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Sun, 28 Jul 2024 19:57:02 +0800
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Subject: [PATCH 179/188] LoongArch: Rework bswap{hi,si,di}2 definition
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Per a gcc-help thread we are generating sub-optimal code for
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__builtin_bswap{32,64}. To fix it:
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- Use a single revb.d instruction for bswapdi2.
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- Use a single revb.2w instruction for bswapsi2 for TARGET_64BIT,
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revb.2h + rotri.w for !TARGET_64BIT.
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- Use a single revb.2h instruction for bswapsi2 (x) r>> 16, and a single
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revb.2w instruction for bswapdi2 (x) r>> 32.
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Unfortunately I cannot figure out a way to make the compiler generate
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revb.4h or revh.{2w,d} instructions.
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gcc/ChangeLog:
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* config/loongarch/loongarch.md (UNSPEC_REVB_2H, UNSPEC_REVB_4H,
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UNSPEC_REVH_D): Remove UNSPECs.
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(revb_4h, revh_d): Remove define_insn.
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(revb_2h): Define as (rotatert:SI (bswap:SI x) 16) instead of
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an UNSPEC.
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(revb_2h_extend, revb_2w, *bswapsi2, bswapdi2): New define_insn.
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(bswapsi2): Change to define_expand. Only expand to revb.2h +
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rotri.w if !TARGET_64BIT.
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(bswapdi2): Change to define_insn of which the output is just a
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revb.d instruction.
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gcc/testsuite/ChangeLog:
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* gcc.target/loongarch/revb.c: New test.
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---
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gcc/config/loongarch/loongarch.md | 79 ++++++++++++-----------
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gcc/testsuite/gcc.target/loongarch/revb.c | 61 +++++++++++++++++
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2 files changed, 104 insertions(+), 36 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/loongarch/revb.c
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diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
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index 1ebcfa0c7..b1c828dba 100644
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--- a/gcc/config/loongarch/loongarch.md
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+++ b/gcc/config/loongarch/loongarch.md
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@@ -20,11 +20,6 @@
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;; <http://www.gnu.org/licenses/>.
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(define_c_enum "unspec" [
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- ;; Integer operations that are too cumbersome to describe directly.
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- UNSPEC_REVB_2H
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- UNSPEC_REVB_4H
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- UNSPEC_REVH_D
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-
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;; Floating-point moves.
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UNSPEC_LOAD_LOW
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UNSPEC_LOAD_HIGH
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@@ -3151,55 +3146,67 @@
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;; Reverse the order of bytes of operand 1 and store the result in operand 0.
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-(define_insn "bswaphi2"
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- [(set (match_operand:HI 0 "register_operand" "=r")
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- (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
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+(define_insn "revb_2h"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ (rotatert:SI (bswap:SI (match_operand:SI 1 "register_operand" "r"))
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+ (const_int 16)))]
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""
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"revb.2h\t%0,%1"
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[(set_attr "type" "shift")])
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-(define_insn_and_split "bswapsi2"
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- [(set (match_operand:SI 0 "register_operand" "=r")
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- (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
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- ""
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- "#"
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- ""
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- [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_REVB_2H))
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- (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))]
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- ""
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- [(set_attr "insn_count" "2")])
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-
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-(define_insn_and_split "bswapdi2"
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+(define_insn "revb_2h_extend"
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[(set (match_operand:DI 0 "register_operand" "=r")
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- (bswap:DI (match_operand:DI 1 "register_operand" "r")))]
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+ (sign_extend:DI
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+ (rotatert:SI
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+ (bswap:SI (match_operand:SI 1 "register_operand" "r"))
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+ (const_int 16))))]
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"TARGET_64BIT"
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- "#"
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- ""
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- [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_REVB_4H))
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- (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_REVH_D))]
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- ""
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- [(set_attr "insn_count" "2")])
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+ "revb.2h\t%0,%1"
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+ [(set_attr "type" "shift")])
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-(define_insn "revb_2h"
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- [(set (match_operand:SI 0 "register_operand" "=r")
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- (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_REVB_2H))]
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+(define_insn "bswaphi2"
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+ [(set (match_operand:HI 0 "register_operand" "=r")
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+ (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
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""
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"revb.2h\t%0,%1"
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[(set_attr "type" "shift")])
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-(define_insn "revb_4h"
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+(define_insn "revb_2w"
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[(set (match_operand:DI 0 "register_operand" "=r")
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- (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_REVB_4H))]
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+ (rotatert:DI (bswap:DI (match_operand:DI 1 "register_operand" "r"))
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+ (const_int 32)))]
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"TARGET_64BIT"
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- "revb.4h\t%0,%1"
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+ "revb.2w\t%0,%1"
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[(set_attr "type" "shift")])
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-(define_insn "revh_d"
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+(define_insn "*bswapsi2"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
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+ "TARGET_64BIT"
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+ "revb.2w\t%0,%1"
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+ [(set_attr "type" "shift")])
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+
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+(define_expand "bswapsi2"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
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+ ""
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+{
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+ if (!TARGET_64BIT)
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+ {
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+ rtx t = gen_reg_rtx (SImode);
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+ emit_insn (gen_revb_2h (t, operands[1]));
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+ emit_insn (gen_rotrsi3 (operands[0], t, GEN_INT (16)));
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+ DONE;
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+ }
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+})
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+
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+(define_insn "bswapdi2"
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[(set (match_operand:DI 0 "register_operand" "=r")
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- (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_REVH_D))]
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+ (bswap:DI (match_operand:DI 1 "register_operand" "r")))]
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"TARGET_64BIT"
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- "revh.d\t%0,%1"
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+ "revb.d\t%0,%1"
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[(set_attr "type" "shift")])
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+
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;;
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;; ....................
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diff --git a/gcc/testsuite/gcc.target/loongarch/revb.c b/gcc/testsuite/gcc.target/loongarch/revb.c
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new file mode 100644
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index 000000000..27a5d0fc7
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/revb.c
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@@ -0,0 +1,61 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */
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+/* { dg-final { check-function-bodies "**" "" } } */
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+
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+/*
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+**t1:
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+** revb.2w \$r4,\$r4
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+** slli.w \$r4,\$r4,0
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+** jr \$r1
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+*/
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+unsigned int
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+t1 (unsigned int x)
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+{
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+ return __builtin_bswap32 (x);
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+}
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+
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+/*
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+**t2:
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+** revb.d \$r4,\$r4
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+** jr \$r1
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+*/
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+unsigned long
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+t2 (unsigned long x)
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+{
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+ return __builtin_bswap64 (x);
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+}
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+
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+/*
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+**t3:
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+** revb.2h \$r4,\$r4
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+** jr \$r1
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+*/
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+unsigned int
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+t3 (unsigned int x)
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+{
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+ return (x >> 8) & 0xff00ff | (x << 8) & 0xff00ff00;
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+}
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+
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+/*
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+**t4:
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+** revb.2w \$r4,\$r4
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+** jr \$r1
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+*/
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+unsigned long
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+t4 (unsigned long x)
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+{
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+ x = __builtin_bswap64 (x);
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+ return x << 32 | x >> 32;
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+}
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+
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+/*
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+**t5:
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+** revb.2h \$r4,\$r4
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+** bstrpick.w \$r4,\$r4,15,0
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+** jr \$r1
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+*/
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+unsigned short
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+t5 (unsigned short x)
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+{
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+ return __builtin_bswap16 (x);
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+}
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--
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2.43.0
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