108 lines
4.8 KiB
Diff
108 lines
4.8 KiB
Diff
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From ccc3ca614bbaa242fe25ec82b903dfcac03fe2de Mon Sep 17 00:00:00 2001
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From: Richard Sandiford <richard.sandiford@arm.com>
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Date: Tue, 17 Oct 2023 23:46:33 +0100
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Subject: [PATCH 105/157] [Backport][SME] aarch64: Put LR save slot first in
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more cases
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Reference: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=773306e9ef4ea1407f89686eb513a50602493666
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Now that the prologue and epilogue code iterates over saved
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registers in offset order, we can put the LR save slot first
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without compromising LDP/STP formation.
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This isn't worthwhile when shadow call stacks are enabled, since the
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first two registers are also push/pop candidates, and LR cannot be
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popped when shadow call stacks are enabled. (LR is instead loaded
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first and compared against the shadow stack's value.)
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But otherwise, it seems better to put the LR save slot first,
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to reduce unnecessary variation with the layout for stack clash
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protection.
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gcc/
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* config/aarch64/aarch64.cc (aarch64_layout_frame): Don't make
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the position of the LR save slot dependent on stack clash
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protection unless shadow call stacks are enabled.
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gcc/testsuite/
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* gcc.target/aarch64/test_frame_2.c: Expect x30 to come before x19.
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* gcc.target/aarch64/test_frame_4.c: Likewise.
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* gcc.target/aarch64/test_frame_7.c: Likewise.
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* gcc.target/aarch64/test_frame_10.c: Likewise.
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---
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gcc/config/aarch64/aarch64.cc | 2 +-
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gcc/testsuite/gcc.target/aarch64/test_frame_10.c | 4 ++--
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gcc/testsuite/gcc.target/aarch64/test_frame_2.c | 4 ++--
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gcc/testsuite/gcc.target/aarch64/test_frame_4.c | 4 ++--
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gcc/testsuite/gcc.target/aarch64/test_frame_7.c | 4 ++--
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5 files changed, 9 insertions(+), 9 deletions(-)
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diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
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index e10c9d763..1c127192d 100644
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--- a/gcc/config/aarch64/aarch64.cc
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+++ b/gcc/config/aarch64/aarch64.cc
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@@ -8920,7 +8920,7 @@ aarch64_layout_frame (void)
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allocate_gpr_slot (R29_REGNUM);
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allocate_gpr_slot (R30_REGNUM);
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}
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- else if (flag_stack_clash_protection
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+ else if ((flag_stack_clash_protection || !frame.is_scs_enabled)
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&& known_eq (frame.reg_offset[R30_REGNUM], SLOT_REQUIRED))
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/* Put the LR save slot first, since it makes a good choice of probe
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for stack clash purposes. The idea is that the link register usually
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diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_10.c b/gcc/testsuite/gcc.target/aarch64/test_frame_10.c
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index c19505082..c54ab2d0c 100644
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--- a/gcc/testsuite/gcc.target/aarch64/test_frame_10.c
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+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_10.c
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@@ -14,6 +14,6 @@
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t_frame_pattern_outgoing (test10, 480, "x19", 24, a[8], a[9], a[10])
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t_frame_run (test10)
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-/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, \[0-9\]+\\\]" 1 } } */
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-/* { dg-final { scan-assembler "ldp\tx19, x30, \\\[sp, \[0-9\]+\\\]" } } */
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+/* { dg-final { scan-assembler-times "stp\tx30, x19, \\\[sp, \[0-9\]+\\\]" 1 } } */
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+/* { dg-final { scan-assembler "ldp\tx30, x19, \\\[sp, \[0-9\]+\\\]" } } */
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diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_2.c b/gcc/testsuite/gcc.target/aarch64/test_frame_2.c
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index 7e5df84cf..0d715314c 100644
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--- a/gcc/testsuite/gcc.target/aarch64/test_frame_2.c
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+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_2.c
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@@ -14,6 +14,6 @@ t_frame_pattern (test2, 200, "x19")
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t_frame_run (test2)
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-/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
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-/* { dg-final { scan-assembler "ldp\tx19, x30, \\\[sp\\\], \[0-9\]+" } } */
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+/* { dg-final { scan-assembler-times "stp\tx30, x19, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
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+/* { dg-final { scan-assembler "ldp\tx30, x19, \\\[sp\\\], \[0-9\]+" } } */
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diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_4.c b/gcc/testsuite/gcc.target/aarch64/test_frame_4.c
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index ed13487a0..b41229c42 100644
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--- a/gcc/testsuite/gcc.target/aarch64/test_frame_4.c
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+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_4.c
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@@ -13,6 +13,6 @@
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t_frame_pattern (test4, 400, "x19")
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t_frame_run (test4)
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-/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
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-/* { dg-final { scan-assembler "ldp\tx19, x30, \\\[sp\\\], \[0-9\]+" } } */
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+/* { dg-final { scan-assembler-times "stp\tx30, x19, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
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+/* { dg-final { scan-assembler "ldp\tx30, x19, \\\[sp\\\], \[0-9\]+" } } */
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diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_7.c b/gcc/testsuite/gcc.target/aarch64/test_frame_7.c
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index 964527949..5702656a5 100644
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--- a/gcc/testsuite/gcc.target/aarch64/test_frame_7.c
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+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_7.c
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@@ -13,6 +13,6 @@
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t_frame_pattern (test7, 700, "x19")
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t_frame_run (test7)
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-/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp]" 1 } } */
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-/* { dg-final { scan-assembler "ldp\tx19, x30, \\\[sp\\\]" } } */
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+/* { dg-final { scan-assembler-times "stp\tx30, x19, \\\[sp]" 1 } } */
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+/* { dg-final { scan-assembler "ldp\tx30, x19, \\\[sp\\\]" } } */
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--
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2.33.0
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