121 lines
4.2 KiB
Diff
121 lines
4.2 KiB
Diff
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From 3bb46830b0f92f54d1ef529796348c0a86504065 Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Fri, 26 Apr 2024 15:59:11 +0800
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Subject: [PATCH 166/188] LoongArch: Add constraints for bit string operation
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define_insn_and_split's [PR114861]
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Without the constrants, the compiler attempts to use a stack slot as the
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target, causing an ICE building the kernel with -Os:
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drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c:3144:1:
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error: could not split insn
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(insn:TI 1764 67 1745
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(set (mem/c:DI (reg/f:DI 3 $r3) [707 %sfp+-80 S8 A64])
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(and:DI (reg/v:DI 28 $r28 [orig:422 raster_config ] [422])
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(const_int -50331649 [0xfffffffffcffffff])))
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"drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c":1386:21 111
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{*bstrins_di_for_mask}
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(nil))
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Add these constrants to fix the issue.
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gcc/ChangeLog:
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PR target/114861
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* config/loongarch/loongarch.md (bstrins_<mode>_for_mask): Add
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constraints for operands.
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(bstrins_<mode>_for_ior_mask): Likewise.
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gcc/testsuite/ChangeLog:
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PR target/114861
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* gcc.target/loongarch/pr114861.c: New test.
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---
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gcc/config/loongarch/loongarch.md | 16 ++++----
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gcc/testsuite/gcc.target/loongarch/pr114861.c | 39 +++++++++++++++++++
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2 files changed, 47 insertions(+), 8 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/loongarch/pr114861.c
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diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
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index 95beb88fe..20494ce8a 100644
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--- a/gcc/config/loongarch/loongarch.md
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+++ b/gcc/config/loongarch/loongarch.md
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@@ -1543,9 +1543,9 @@
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(set_attr "mode" "<MODE>")])
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(define_insn_and_split "*bstrins_<mode>_for_mask"
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- [(set (match_operand:GPR 0 "register_operand")
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- (and:GPR (match_operand:GPR 1 "register_operand")
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- (match_operand:GPR 2 "ins_zero_bitmask_operand")))]
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+ [(set (match_operand:GPR 0 "register_operand" "=r")
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+ (and:GPR (match_operand:GPR 1 "register_operand" "r")
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+ (match_operand:GPR 2 "ins_zero_bitmask_operand" "i")))]
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""
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"#"
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""
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@@ -1563,11 +1563,11 @@
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})
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(define_insn_and_split "*bstrins_<mode>_for_ior_mask"
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- [(set (match_operand:GPR 0 "register_operand")
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- (ior:GPR (and:GPR (match_operand:GPR 1 "register_operand")
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- (match_operand:GPR 2 "const_int_operand"))
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- (and:GPR (match_operand:GPR 3 "register_operand")
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- (match_operand:GPR 4 "const_int_operand"))))]
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+ [(set (match_operand:GPR 0 "register_operand" "=r")
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+ (ior:GPR (and:GPR (match_operand:GPR 1 "register_operand" "r")
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+ (match_operand:GPR 2 "const_int_operand" "i"))
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+ (and:GPR (match_operand:GPR 3 "register_operand" "r")
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+ (match_operand:GPR 4 "const_int_operand" "i"))))]
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"loongarch_pre_reload_split ()
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&& loongarch_use_bstrins_for_ior_with_mask (<MODE>mode, operands)"
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"#"
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diff --git a/gcc/testsuite/gcc.target/loongarch/pr114861.c b/gcc/testsuite/gcc.target/loongarch/pr114861.c
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new file mode 100644
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index 000000000..e6507c406
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/pr114861.c
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@@ -0,0 +1,39 @@
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+/* PR114861: ICE building the kernel with -Os
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+ Reduced from linux/fs/ntfs3/attrib.c at revision c942a0cd3603. */
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+/* { dg-do compile } */
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+/* { dg-options "-Os -march=loongarch64 -msoft-float -mabi=lp64s" } */
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+
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+long evcn, attr_collapse_range_vbo, attr_collapse_range_bytes;
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+unsigned short flags;
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+int attr_collapse_range_ni_0_0;
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+int *attr_collapse_range_mi;
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+unsigned attr_collapse_range_svcn, attr_collapse_range_vcn1;
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+void ni_insert_nonresident (unsigned, unsigned short, int **);
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+int mi_pack_runs (int);
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+int
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+attr_collapse_range (void)
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+{
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+ _Bool __trans_tmp_1;
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+ int run = attr_collapse_range_ni_0_0;
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+ unsigned evcn1, vcn, end;
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+ short a_flags = flags;
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+ __trans_tmp_1 = flags & (32768 | 1);
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+ if (__trans_tmp_1)
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+ return 2;
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+ vcn = attr_collapse_range_vbo;
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+ end = attr_collapse_range_bytes;
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+ evcn1 = evcn;
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+ for (;;)
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+ if (attr_collapse_range_svcn >= end)
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+ {
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+ unsigned eat, next_svcn = mi_pack_runs (42);
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+ attr_collapse_range_vcn1 = (vcn ? vcn : attr_collapse_range_svcn);
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+ eat = (0 < end) - attr_collapse_range_vcn1;
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+ mi_pack_runs (run - eat);
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+ if (next_svcn + eat)
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+ ni_insert_nonresident (evcn1 - eat - next_svcn, a_flags,
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+ &attr_collapse_range_mi);
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+ }
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+ else
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+ return 42;
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+}
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--
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2.43.0
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