133 lines
3.9 KiB
Diff
133 lines
3.9 KiB
Diff
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From b1947829a5949a37db09bc23681e44c8479bd404 Mon Sep 17 00:00:00 2001
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From: Chenghui Pan <panchenghui@loongson.cn>
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Date: Fri, 22 Dec 2023 16:22:03 +0800
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Subject: [PATCH 086/188] LoongArch: Fix insn output of vec_concat templates
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for LASX.
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When investigaing failure of gcc.dg/vect/slp-reduc-sad.c, following
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instruction block are being generated by vec_concatv32qi (which is
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generated by vec_initv32qiv16qi) at entrance of foo() function:
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vldx $vr3,$r5,$r6
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vld $vr2,$r5,0
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xvpermi.q $xr2,$xr3,0x20
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causes the reversion of vec_initv32qiv16qi operation's high and
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low 128-bit part.
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According to other target's similar impl and LSX impl for following
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RTL representation, current definition in lasx.md of "vec_concat<mode>"
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are wrong:
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(set (op0) (vec_concat (op1) (op2)))
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For correct behavior, the last argument of xvpermi.q should be 0x02
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instead of 0x20. This patch fixes this issue and cleanup the vec_concat
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template impl.
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gcc/ChangeLog:
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* config/loongarch/lasx.md (vec_concatv4di): Delete.
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(vec_concatv8si): Delete.
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(vec_concatv16hi): Delete.
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(vec_concatv32qi): Delete.
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(vec_concatv4df): Delete.
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(vec_concatv8sf): Delete.
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(vec_concat<mode>): New template with insn output fixed.
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---
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gcc/config/loongarch/lasx.md | 74 ++++--------------------------------
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1 file changed, 7 insertions(+), 67 deletions(-)
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diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
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index 9ca3f9278..46150f2fb 100644
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--- a/gcc/config/loongarch/lasx.md
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+++ b/gcc/config/loongarch/lasx.md
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@@ -577,77 +577,17 @@
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[(set_attr "type" "simd_insert")
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(set_attr "mode" "<MODE>")])
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-(define_insn "vec_concatv4di"
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- [(set (match_operand:V4DI 0 "register_operand" "=f")
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- (vec_concat:V4DI
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- (match_operand:V2DI 1 "register_operand" "0")
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- (match_operand:V2DI 2 "register_operand" "f")))]
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- "ISA_HAS_LASX"
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-{
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- return "xvpermi.q\t%u0,%u2,0x20";
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-}
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- [(set_attr "type" "simd_splat")
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- (set_attr "mode" "V4DI")])
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-
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-(define_insn "vec_concatv8si"
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- [(set (match_operand:V8SI 0 "register_operand" "=f")
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- (vec_concat:V8SI
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- (match_operand:V4SI 1 "register_operand" "0")
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- (match_operand:V4SI 2 "register_operand" "f")))]
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- "ISA_HAS_LASX"
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-{
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- return "xvpermi.q\t%u0,%u2,0x20";
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-}
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- [(set_attr "type" "simd_splat")
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- (set_attr "mode" "V4DI")])
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-
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-(define_insn "vec_concatv16hi"
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- [(set (match_operand:V16HI 0 "register_operand" "=f")
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- (vec_concat:V16HI
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- (match_operand:V8HI 1 "register_operand" "0")
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- (match_operand:V8HI 2 "register_operand" "f")))]
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- "ISA_HAS_LASX"
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-{
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- return "xvpermi.q\t%u0,%u2,0x20";
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-}
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- [(set_attr "type" "simd_splat")
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- (set_attr "mode" "V4DI")])
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-
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-(define_insn "vec_concatv32qi"
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- [(set (match_operand:V32QI 0 "register_operand" "=f")
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- (vec_concat:V32QI
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- (match_operand:V16QI 1 "register_operand" "0")
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- (match_operand:V16QI 2 "register_operand" "f")))]
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- "ISA_HAS_LASX"
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-{
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- return "xvpermi.q\t%u0,%u2,0x20";
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-}
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- [(set_attr "type" "simd_splat")
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- (set_attr "mode" "V4DI")])
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-
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-(define_insn "vec_concatv4df"
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- [(set (match_operand:V4DF 0 "register_operand" "=f")
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- (vec_concat:V4DF
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- (match_operand:V2DF 1 "register_operand" "0")
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- (match_operand:V2DF 2 "register_operand" "f")))]
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- "ISA_HAS_LASX"
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-{
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- return "xvpermi.q\t%u0,%u2,0x20";
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-}
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- [(set_attr "type" "simd_splat")
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- (set_attr "mode" "V4DF")])
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-
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-(define_insn "vec_concatv8sf"
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- [(set (match_operand:V8SF 0 "register_operand" "=f")
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- (vec_concat:V8SF
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- (match_operand:V4SF 1 "register_operand" "0")
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- (match_operand:V4SF 2 "register_operand" "f")))]
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+(define_insn "vec_concat<mode>"
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+ [(set (match_operand:LASX 0 "register_operand" "=f")
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+ (vec_concat:LASX
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+ (match_operand:<VHMODE256_ALL> 1 "register_operand" "0")
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+ (match_operand:<VHMODE256_ALL> 2 "register_operand" "f")))]
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"ISA_HAS_LASX"
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{
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- return "xvpermi.q\t%u0,%u2,0x20";
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+ return "xvpermi.q\t%u0,%u2,0x02";
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}
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[(set_attr "type" "simd_splat")
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- (set_attr "mode" "V4DI")])
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+ (set_attr "mode" "<MODE>")])
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;; xshuf.w
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(define_insn "lasx_xvperm_<lasxfmt_f_wd>"
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--
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2.43.0
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