76 lines
2.6 KiB
Diff
76 lines
2.6 KiB
Diff
From e19c5ba24839d7446f1874b0b33bd61e27e36905 Mon Sep 17 00:00:00 2001
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From: Jiahao Xu <xujiahao@loongson.cn>
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Date: Wed, 24 Jan 2024 17:19:13 +0800
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Subject: [PATCH 119/188] LoongArch: Remove vec_concatz<mode> pattern.
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It is incorrect to use vld/vori to implement the vec_concatz<mode> because when the LSX
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instruction is used to update the value of the vector register, the upper 128 bits of
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the vector register will not be zeroed.
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gcc/ChangeLog:
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* config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
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* config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
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---
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gcc/config/loongarch/lasx.md | 15 ---------------
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gcc/config/loongarch/loongarch.cc | 17 ++++++-----------
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2 files changed, 6 insertions(+), 26 deletions(-)
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diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
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index fdfd65e4a..a5128c30c 100644
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--- a/gcc/config/loongarch/lasx.md
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+++ b/gcc/config/loongarch/lasx.md
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@@ -582,21 +582,6 @@
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[(set_attr "type" "simd_insert")
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(set_attr "mode" "<MODE>")])
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-(define_insn "@vec_concatz<mode>"
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- [(set (match_operand:LASX 0 "register_operand" "=f")
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- (vec_concat:LASX
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- (match_operand:<VHMODE256_ALL> 1 "nonimmediate_operand")
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- (match_operand:<VHMODE256_ALL> 2 "const_0_operand")))]
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- "ISA_HAS_LASX"
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-{
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- if (MEM_P (operands[1]))
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- return "vld\t%w0,%1";
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- else
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- return "vori.b\t%w0,%w1,0";
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-}
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- [(set_attr "type" "simd_splat")
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- (set_attr "mode" "<MODE>")])
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-
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(define_insn "vec_concat<mode>"
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[(set (match_operand:LASX 0 "register_operand" "=f")
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(vec_concat:LASX
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diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
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index 9cdd4ed15..9bd931549 100644
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--- a/gcc/config/loongarch/loongarch.cc
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+++ b/gcc/config/loongarch/loongarch.cc
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@@ -9912,17 +9912,12 @@ loongarch_expand_vector_group_init (rtx target, rtx vals)
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gcc_unreachable ();
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}
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- if (high == CONST0_RTX (half_mode))
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- emit_insn (gen_vec_concatz (vmode, target, low, high));
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- else
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- {
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- if (!register_operand (low, half_mode))
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- low = force_reg (half_mode, low);
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- if (!register_operand (high, half_mode))
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- high = force_reg (half_mode, high);
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- emit_insn (gen_rtx_SET (target,
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- gen_rtx_VEC_CONCAT (vmode, low, high)));
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- }
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+ if (!register_operand (low, half_mode))
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+ low = force_reg (half_mode, low);
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+ if (!register_operand (high, half_mode))
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+ high = force_reg (half_mode, high);
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+ emit_insn (gen_rtx_SET (target,
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+ gen_rtx_VEC_CONCAT (vmode, low, high)));
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}
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/* Expand initialization of a vector which has all same elements. */
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--
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2.43.0
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