73 lines
3.1 KiB
Diff
73 lines
3.1 KiB
Diff
From 8310c0df319a86bc2f63b8d3198dd1c394827bac Mon Sep 17 00:00:00 2001
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From: Richard Sandiford <richard.sandiford@arm.com>
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Date: Tue, 5 Dec 2023 10:11:27 +0000
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Subject: [PATCH 109/157] [Backport][SME] aarch64: Add a VNx1TI mode
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Reference: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=80fc055cf00fee4b1f9f19f77c8880b12226e086
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Although TI isn't really a native SVE element mode, it's convenient
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for SME if we define VNx1TI anyway, so that it can be used to
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distinguish .Q ZA operations from others. It's purely an RTL
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convenience and isn't (yet) a valid storage mode.
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gcc/
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* config/aarch64/aarch64-modes.def: Add VNx1TI.
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---
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gcc/config/aarch64/aarch64-modes.def | 21 ++++++++++++++-------
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1 file changed, 14 insertions(+), 7 deletions(-)
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diff --git a/gcc/config/aarch64/aarch64-modes.def b/gcc/config/aarch64/aarch64-modes.def
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index 8f399225a..8fa66fdb3 100644
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--- a/gcc/config/aarch64/aarch64-modes.def
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+++ b/gcc/config/aarch64/aarch64-modes.def
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@@ -146,7 +146,7 @@ ADV_SIMD_Q_REG_STRUCT_MODES (4, V4x16, V4x8, V4x4, V4x2)
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for 8-bit, 16-bit, 32-bit and 64-bit elements respectively. It isn't
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strictly necessary to set the alignment here, since the default would
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be clamped to BIGGEST_ALIGNMENT anyhow, but it seems clearer. */
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-#define SVE_MODES(NVECS, VB, VH, VS, VD) \
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+#define SVE_MODES(NVECS, VB, VH, VS, VD, VT) \
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VECTOR_MODES_WITH_PREFIX (VNx, INT, 16 * NVECS, NVECS == 1 ? 1 : 4); \
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VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 16 * NVECS, NVECS == 1 ? 1 : 4); \
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\
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@@ -154,6 +154,7 @@ ADV_SIMD_Q_REG_STRUCT_MODES (4, V4x16, V4x8, V4x4, V4x2)
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ADJUST_NUNITS (VH##HI, aarch64_sve_vg * NVECS * 4); \
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ADJUST_NUNITS (VS##SI, aarch64_sve_vg * NVECS * 2); \
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ADJUST_NUNITS (VD##DI, aarch64_sve_vg * NVECS); \
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+ ADJUST_NUNITS (VT##TI, exact_div (aarch64_sve_vg * NVECS, 2)); \
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ADJUST_NUNITS (VH##BF, aarch64_sve_vg * NVECS * 4); \
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ADJUST_NUNITS (VH##HF, aarch64_sve_vg * NVECS * 4); \
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ADJUST_NUNITS (VS##SF, aarch64_sve_vg * NVECS * 2); \
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@@ -163,17 +164,23 @@ ADV_SIMD_Q_REG_STRUCT_MODES (4, V4x16, V4x8, V4x4, V4x2)
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ADJUST_ALIGNMENT (VH##HI, 16); \
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ADJUST_ALIGNMENT (VS##SI, 16); \
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ADJUST_ALIGNMENT (VD##DI, 16); \
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+ ADJUST_ALIGNMENT (VT##TI, 16); \
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ADJUST_ALIGNMENT (VH##BF, 16); \
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ADJUST_ALIGNMENT (VH##HF, 16); \
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ADJUST_ALIGNMENT (VS##SF, 16); \
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ADJUST_ALIGNMENT (VD##DF, 16);
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-/* Give SVE vectors the names normally used for 256-bit vectors.
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- The actual number depends on command-line flags. */
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-SVE_MODES (1, VNx16, VNx8, VNx4, VNx2)
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-SVE_MODES (2, VNx32, VNx16, VNx8, VNx4)
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-SVE_MODES (3, VNx48, VNx24, VNx12, VNx6)
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-SVE_MODES (4, VNx64, VNx32, VNx16, VNx8)
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+/* Give SVE vectors names of the form VNxX, where X describes what is
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+ stored in each 128-bit unit. The actual size of the mode depends
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+ on command-line flags.
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+
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+ VNx1TI isn't really a native SVE mode, but it can be useful in some
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+ limited situations. */
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+VECTOR_MODE_WITH_PREFIX (VNx, INT, TI, 1, 1);
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+SVE_MODES (1, VNx16, VNx8, VNx4, VNx2, VNx1)
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+SVE_MODES (2, VNx32, VNx16, VNx8, VNx4, VNx2)
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+SVE_MODES (3, VNx48, VNx24, VNx12, VNx6, VNx3)
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+SVE_MODES (4, VNx64, VNx32, VNx16, VNx8, VNx4)
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/* Partial SVE vectors:
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--
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2.33.0
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