35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
From 7f4a912da99f5787c88b275b83ee547c9e1aa3d7 Mon Sep 17 00:00:00 2001
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From: Lulu Cheng <chenglulu@loongson.cn>
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Date: Mon, 23 Oct 2023 09:07:32 +0800
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Subject: [PATCH 014/188] LoongArch: Define macro CLEAR_INSN_CACHE.
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LoongArch's microstructure ensures cache consistency by hardware.
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Due to out-of-order execution, "ibar" is required to ensure the visibility of the
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store (invalidated icache) executed by this CPU before "ibar" (to the instance).
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"ibar" will not invalidate the icache, so the start and end parameters are not Affect
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"ibar" performance.
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gcc/ChangeLog:
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* config/loongarch/loongarch.h (CLEAR_INSN_CACHE): New definition.
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---
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gcc/config/loongarch/loongarch.h | 5 +++++
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1 file changed, 5 insertions(+)
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diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h
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index 572b538be..f7ddfc452 100644
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--- a/gcc/config/loongarch/loongarch.h
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+++ b/gcc/config/loongarch/loongarch.h
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@@ -1231,3 +1231,8 @@ struct GTY (()) machine_function
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(TARGET_HARD_FLOAT_ABI ? (TARGET_DOUBLE_FLOAT_ABI ? 8 : 4) : 0)
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#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
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+
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+/* LoongArch maintains ICache/DCache coherency by hardware,
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+ we just need "ibar" to avoid instruction hazard here. */
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+#undef CLEAR_INSN_CACHE
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+#define CLEAR_INSN_CACHE(beg, end) __builtin_loongarch_ibar (0)
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--
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2.43.0
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