123 lines
4.0 KiB
Diff
123 lines
4.0 KiB
Diff
From 659b51a6aed60f389009eff1e04645a47e55a45c Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Sat, 3 Feb 2024 03:16:14 +0800
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Subject: [PATCH 134/188] LoongArch: Fix wrong LSX FP vector negation
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We expanded (neg x) to (minus const0 x) for LSX FP vectors, this is
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wrong because -0.0 is not 0 - 0.0. This causes some Python tests to
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fail when Python is built with LSX enabled.
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Use the vbitrevi.{d/w} instructions to simply reverse the sign bit
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instead. We are already doing this for LASX and now we can unify them
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into simd.md.
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gcc/ChangeLog:
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* config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
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incorrect expand.
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* config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
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(elmsgnbit): Likewise.
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(neg<mode:FVEC>2): New define_insn.
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* config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
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are now instantiated in simd.md.
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---
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gcc/config/loongarch/lasx.md | 16 ----------------
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gcc/config/loongarch/lsx.md | 11 -----------
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gcc/config/loongarch/simd.md | 18 ++++++++++++++++++
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3 files changed, 18 insertions(+), 27 deletions(-)
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diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
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index 946811e1a..38f35bad6 100644
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--- a/gcc/config/loongarch/lasx.md
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+++ b/gcc/config/loongarch/lasx.md
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@@ -3028,22 +3028,6 @@
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[(set_attr "type" "simd_logic")
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(set_attr "mode" "V8SF")])
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-(define_insn "negv4df2"
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- [(set (match_operand:V4DF 0 "register_operand" "=f")
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- (neg:V4DF (match_operand:V4DF 1 "register_operand" "f")))]
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- "ISA_HAS_LASX"
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- "xvbitrevi.d\t%u0,%u1,63"
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- [(set_attr "type" "simd_logic")
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- (set_attr "mode" "V4DF")])
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-
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-(define_insn "negv8sf2"
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- [(set (match_operand:V8SF 0 "register_operand" "=f")
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- (neg:V8SF (match_operand:V8SF 1 "register_operand" "f")))]
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- "ISA_HAS_LASX"
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- "xvbitrevi.w\t%u0,%u1,31"
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- [(set_attr "type" "simd_logic")
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- (set_attr "mode" "V8SF")])
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-
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(define_insn "xvfmadd<mode>4"
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[(set (match_operand:FLASX 0 "register_operand" "=f")
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(fma:FLASX (match_operand:FLASX 1 "register_operand" "f")
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diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
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index 612377436..d5aa3f46f 100644
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--- a/gcc/config/loongarch/lsx.md
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+++ b/gcc/config/loongarch/lsx.md
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@@ -728,17 +728,6 @@
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DONE;
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})
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-(define_expand "neg<mode>2"
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- [(set (match_operand:FLSX 0 "register_operand")
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- (neg:FLSX (match_operand:FLSX 1 "register_operand")))]
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- "ISA_HAS_LSX"
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-{
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- rtx reg = gen_reg_rtx (<MODE>mode);
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- emit_move_insn (reg, CONST0_RTX (<MODE>mode));
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- emit_insn (gen_sub<mode>3 (operands[0], reg, operands[1]));
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- DONE;
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-})
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-
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(define_expand "lsx_vrepli<mode>"
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[(match_operand:ILSX 0 "register_operand")
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(match_operand 1 "const_imm10_operand")]
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diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md
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index 8ac1d75a8..00d4c7831 100644
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--- a/gcc/config/loongarch/simd.md
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+++ b/gcc/config/loongarch/simd.md
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@@ -85,12 +85,21 @@
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(define_mode_attr simdifmt_for_f [(V2DF "l") (V4DF "l")
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(V4SF "w") (V8SF "w")])
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+;; Suffix for integer mode in LSX or LASX instructions to operating FP
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+;; vectors using integer vector operations.
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+(define_mode_attr simdfmt_as_i [(V2DF "d") (V4DF "d")
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+ (V4SF "w") (V8SF "w")])
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+
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;; Size of vector elements in bits.
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(define_mode_attr elmbits [(V2DI "64") (V4DI "64")
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(V4SI "32") (V8SI "32")
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(V8HI "16") (V16HI "16")
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(V16QI "8") (V32QI "8")])
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+;; The index of sign bit in FP vector elements.
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+(define_mode_attr elmsgnbit [(V2DF "63") (V4DF "63")
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+ (V4SF "31") (V8SF "31")])
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+
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;; This attribute is used to form an immediate operand constraint using
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;; "const_<bitimm>_operand".
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(define_mode_attr bitimm [(V16QI "uimm3") (V32QI "uimm3")
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@@ -457,6 +466,15 @@
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DONE;
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})
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+;; FP negation.
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+(define_insn "neg<mode>2"
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+ [(set (match_operand:FVEC 0 "register_operand" "=f")
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+ (neg:FVEC (match_operand:FVEC 1 "register_operand" "f")))]
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+ ""
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+ "<x>vbitrevi.<simdfmt_as_i>\t%<wu>0,%<wu>1,<elmsgnbit>"
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+ [(set_attr "type" "simd_logic")
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+ (set_attr "mode" "<MODE>")])
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+
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; The LoongArch SX Instructions.
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(include "lsx.md")
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--
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2.43.0
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