250 lines
8.6 KiB
Diff
250 lines
8.6 KiB
Diff
From a75609d90f506709e4af26701aa4fb6adce00700 Mon Sep 17 00:00:00 2001
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From: Lulu Cheng <chenglulu@loongson.cn>
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Date: Thu, 4 Jul 2024 15:00:40 +0800
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Subject: [PATCH 175/188] LoongArch: Remove unreachable codes.
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gcc/ChangeLog:
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* config/loongarch/loongarch.cc
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(loongarch_split_move): Delete.
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(loongarch_hard_regno_mode_ok_uncached): Likewise.
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* config/loongarch/loongarch.md
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(move_doubleword_fpr<mode>): Likewise.
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(load_low<mode>): Likewise.
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(load_high<mode>): Likewise.
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(store_word<mode>): Likewise.
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(movgr2frh<mode>): Likewise.
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(movfrh2gr<mode>): Likewise.
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---
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gcc/config/loongarch/loongarch.cc | 47 +++----------
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gcc/config/loongarch/loongarch.md | 109 ------------------------------
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2 files changed, 8 insertions(+), 148 deletions(-)
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diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
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index b78512e0e..260dd7b5f 100644
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--- a/gcc/config/loongarch/loongarch.cc
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+++ b/gcc/config/loongarch/loongarch.cc
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@@ -4459,42 +4459,13 @@ loongarch_split_move_p (rtx dest, rtx src)
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void
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loongarch_split_move (rtx dest, rtx src)
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{
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- rtx low_dest;
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-
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gcc_checking_assert (loongarch_split_move_p (dest, src));
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if (LSX_SUPPORTED_MODE_P (GET_MODE (dest)))
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loongarch_split_128bit_move (dest, src);
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else if (LASX_SUPPORTED_MODE_P (GET_MODE (dest)))
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loongarch_split_256bit_move (dest, src);
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- else if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
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- {
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- if (!TARGET_64BIT && GET_MODE (dest) == DImode)
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- emit_insn (gen_move_doubleword_fprdi (dest, src));
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- else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
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- emit_insn (gen_move_doubleword_fprdf (dest, src));
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- else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
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- emit_insn (gen_move_doubleword_fprtf (dest, src));
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- else
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- gcc_unreachable ();
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- }
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else
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- {
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- /* The operation can be split into two normal moves. Decide in
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- which order to do them. */
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- low_dest = loongarch_subword (dest, false);
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- if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src))
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- {
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- loongarch_emit_move (loongarch_subword (dest, true),
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- loongarch_subword (src, true));
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- loongarch_emit_move (low_dest, loongarch_subword (src, false));
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- }
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- else
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- {
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- loongarch_emit_move (low_dest, loongarch_subword (src, false));
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- loongarch_emit_move (loongarch_subword (dest, true),
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- loongarch_subword (src, true));
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- }
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- }
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+ gcc_unreachable ();
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}
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/* Check if adding an integer constant value for a specific mode can be
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@@ -6743,20 +6714,18 @@ loongarch_hard_regno_mode_ok_uncached (unsigned int regno, machine_mode mode)
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size = GET_MODE_SIZE (mode);
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mclass = GET_MODE_CLASS (mode);
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- if (GP_REG_P (regno) && !LSX_SUPPORTED_MODE_P (mode)
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+ if (GP_REG_P (regno)
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+ && !LSX_SUPPORTED_MODE_P (mode)
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&& !LASX_SUPPORTED_MODE_P (mode))
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return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
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- /* For LSX, allow TImode and 128-bit vector modes in all FPR. */
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- if (FP_REG_P (regno) && LSX_SUPPORTED_MODE_P (mode))
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- return true;
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-
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- /* FIXED ME: For LASX, allow TImode and 256-bit vector modes in all FPR. */
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- if (FP_REG_P (regno) && LASX_SUPPORTED_MODE_P (mode))
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- return true;
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-
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if (FP_REG_P (regno))
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{
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+ /* Allow 128-bit or 256-bit vector modes in all FPR. */
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+ if (LSX_SUPPORTED_MODE_P (mode)
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+ || LASX_SUPPORTED_MODE_P (mode))
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+ return true;
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+
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if (mclass == MODE_FLOAT
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|| mclass == MODE_COMPLEX_FLOAT
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|| mclass == MODE_VECTOR_FLOAT)
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diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
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index 55a759850..16f9f37c8 100644
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--- a/gcc/config/loongarch/loongarch.md
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+++ b/gcc/config/loongarch/loongarch.md
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@@ -400,9 +400,6 @@
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;; 64-bit modes for which we provide move patterns.
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(define_mode_iterator MOVE64 [DI DF])
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-;; 128-bit modes for which we provide move patterns on 64-bit targets.
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-(define_mode_iterator MOVE128 [TI TF])
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-
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;; Iterator for sub-32-bit integer modes.
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(define_mode_iterator SHORT [QI HI])
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@@ -421,12 +418,6 @@
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(define_mode_iterator ANYFI [(SI "TARGET_HARD_FLOAT")
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(DI "TARGET_DOUBLE_FLOAT")])
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-;; A mode for which moves involving FPRs may need to be split.
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-(define_mode_iterator SPLITF
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- [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
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- (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
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- (TF "TARGET_64BIT && TARGET_DOUBLE_FLOAT")])
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-
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;; A mode for anything with 32 bits or more, and able to be loaded with
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;; the same addressing mode as ld.w.
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(define_mode_iterator LD_AT_LEAST_32_BIT [GPR ANYF])
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@@ -2421,41 +2412,6 @@
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[(set_attr "move_type" "move,load,store")
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(set_attr "mode" "DF")])
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-;; Emit a doubleword move in which exactly one of the operands is
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-;; a floating-point register. We can't just emit two normal moves
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-;; because of the constraints imposed by the FPU register model;
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-;; see loongarch_can_change_mode_class for details. Instead, we keep
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-;; the FPR whole and use special patterns to refer to each word of
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-;; the other operand.
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-
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-(define_expand "move_doubleword_fpr<mode>"
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- [(set (match_operand:SPLITF 0)
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- (match_operand:SPLITF 1))]
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- ""
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-{
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- if (FP_REG_RTX_P (operands[0]))
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- {
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- rtx low = loongarch_subword (operands[1], 0);
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- rtx high = loongarch_subword (operands[1], 1);
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- emit_insn (gen_load_low<mode> (operands[0], low));
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- if (!TARGET_64BIT)
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- emit_insn (gen_movgr2frh<mode> (operands[0], high, operands[0]));
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- else
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- emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
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- }
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- else
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- {
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- rtx low = loongarch_subword (operands[0], 0);
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- rtx high = loongarch_subword (operands[0], 1);
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- emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
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- if (!TARGET_64BIT)
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- emit_insn (gen_movfrh2gr<mode> (high, operands[1]));
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- else
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- emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
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- }
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- DONE;
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-})
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-
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;; Clear one FCC register
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(define_expand "movfcc"
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@@ -2742,49 +2698,6 @@
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[(set_attr "type" "fcvt")
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(set_attr "mode" "<ANYF:MODE>")])
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-;; Load the low word of operand 0 with operand 1.
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-(define_insn "load_low<mode>"
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- [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
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- (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "rJ,m")]
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- UNSPEC_LOAD_LOW))]
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- "TARGET_HARD_FLOAT"
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-{
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- operands[0] = loongarch_subword (operands[0], 0);
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- return loongarch_output_move (operands[0], operands[1]);
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-}
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- [(set_attr "move_type" "mgtf,fpload")
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- (set_attr "mode" "<HALFMODE>")])
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-
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-;; Load the high word of operand 0 from operand 1, preserving the value
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-;; in the low word.
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-(define_insn "load_high<mode>"
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- [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
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- (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "rJ,m")
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- (match_operand:SPLITF 2 "register_operand" "0,0")]
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- UNSPEC_LOAD_HIGH))]
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- "TARGET_HARD_FLOAT"
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-{
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- operands[0] = loongarch_subword (operands[0], 1);
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- return loongarch_output_move (operands[0], operands[1]);
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-}
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- [(set_attr "move_type" "mgtf,fpload")
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- (set_attr "mode" "<HALFMODE>")])
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-
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-;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
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-;; high word and 0 to store the low word.
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-(define_insn "store_word<mode>"
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- [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=r,m")
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- (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
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- (match_operand 2 "const_int_operand")]
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- UNSPEC_STORE_WORD))]
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- "TARGET_HARD_FLOAT"
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-{
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- operands[1] = loongarch_subword (operands[1], INTVAL (operands[2]));
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- return loongarch_output_move (operands[0], operands[1]);
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-}
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- [(set_attr "move_type" "mftg,fpstore")
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- (set_attr "mode" "<HALFMODE>")])
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-
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;; Thread-Local Storage
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(define_insn "@got_load_tls_desc<mode>"
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@@ -2876,28 +2789,6 @@
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(const_int 4)
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(const_int 2)))])
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-;; Move operand 1 to the high word of operand 0 using movgr2frh.w, preserving the
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-;; value in the low word.
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-(define_insn "movgr2frh<mode>"
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- [(set (match_operand:SPLITF 0 "register_operand" "=f")
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- (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "rJ")
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- (match_operand:SPLITF 2 "register_operand" "0")]
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- UNSPEC_MOVGR2FRH))]
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- "TARGET_DOUBLE_FLOAT"
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- "movgr2frh.w\t%z1,%0"
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- [(set_attr "move_type" "mgtf")
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- (set_attr "mode" "<HALFMODE>")])
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-
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-;; Move high word of operand 1 to operand 0 using movfrh2gr.s.
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-(define_insn "movfrh2gr<mode>"
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- [(set (match_operand:<HALFMODE> 0 "register_operand" "=r")
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- (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
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- UNSPEC_MOVFRH2GR))]
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- "TARGET_DOUBLE_FLOAT"
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- "movfrh2gr.s\t%0,%1"
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- [(set_attr "move_type" "mftg")
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- (set_attr "mode" "<HALFMODE>")])
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-
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;; Expand in-line code to clear the instruction cache between operand[0] and
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;; operand[1].
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--
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2.43.0
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