331 lines
12 KiB
Diff
331 lines
12 KiB
Diff
From c097d9ffc7dd8f90f78eb3b994f3691f4c8f812d Mon Sep 17 00:00:00 2001
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From: Richard Sandiford <richard.sandiford@arm.com>
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Date: Tue, 5 Dec 2023 10:11:23 +0000
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Subject: [PATCH 076/157] [Backport][SME] aarch64: Add +sme
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Reference: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=7e04bd1fadf3410c3d24b56f650a52ff53d01a3c
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This patch adds the +sme ISA feature and requires it to be present
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when compiling arm_streaming code. (arm_streaming_compatible code
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does not necessarily assume the presence of SME. It just has to
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work when SME is present and streaming mode is enabled.)
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gcc/
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* doc/invoke.texi: Document SME.
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* doc/sourcebuild.texi: Document aarch64_sve.
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* config/aarch64/aarch64-option-extensions.def (sme): Define.
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* config/aarch64/aarch64.h (AARCH64_ISA_SME): New macro.
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(TARGET_SME): Likewise.
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* config/aarch64/aarch64.cc (aarch64_override_options_internal):
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Ensure that SME is present when compiling streaming code.
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gcc/testsuite/
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* lib/target-supports.exp (check_effective_target_aarch64_sme): New
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target test.
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* gcc.target/aarch64/sme/aarch64-sme.exp: Force SME to be enabled
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if it isn't by default.
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* g++.target/aarch64/sme/aarch64-sme.exp: Likewise.
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* gcc.target/aarch64/sme/streaming_mode_3.c: New test.
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---
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.../aarch64/aarch64-option-extensions.def | 2 +
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gcc/config/aarch64/aarch64.cc | 33 ++++++++++
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gcc/config/aarch64/aarch64.h | 5 ++
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gcc/doc/invoke.texi | 2 +
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gcc/doc/sourcebuild.texi | 2 +
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.../g++.target/aarch64/sme/aarch64-sme.exp | 10 ++-
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.../gcc.target/aarch64/sme/aarch64-sme.exp | 10 ++-
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.../gcc.target/aarch64/sme/streaming_mode_3.c | 63 +++++++++++++++++++
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.../gcc.target/aarch64/sme/streaming_mode_4.c | 22 +++++++
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gcc/testsuite/lib/target-supports.exp | 12 ++++
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10 files changed, 157 insertions(+), 4 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_3.c
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create mode 100644 gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_4.c
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diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
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index bdf4baf30..faee64a79 100644
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--- a/gcc/config/aarch64/aarch64-option-extensions.def
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+++ b/gcc/config/aarch64/aarch64-option-extensions.def
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@@ -149,4 +149,6 @@ AARCH64_OPT_EXTENSION("ls64", LS64, (), (), (), "")
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AARCH64_OPT_EXTENSION("mops", MOPS, (), (), (), "")
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+AARCH64_OPT_EXTENSION("sme", SME, (BF16, SVE2), (), (), "sme")
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+
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#undef AARCH64_OPT_EXTENSION
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diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
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index 904166b21..8f8395201 100644
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--- a/gcc/config/aarch64/aarch64.cc
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+++ b/gcc/config/aarch64/aarch64.cc
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@@ -11648,6 +11648,23 @@ aarch64_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
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return true;
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}
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+/* Implement TARGET_START_CALL_ARGS. */
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+
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+static void
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+aarch64_start_call_args (cumulative_args_t ca_v)
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+{
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+ CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
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+
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+ if (!TARGET_SME && (ca->isa_mode & AARCH64_FL_SM_ON))
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+ {
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+ error ("calling a streaming function requires the ISA extension %qs",
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+ "sme");
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+ inform (input_location, "you can enable %qs using the command-line"
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+ " option %<-march%>, or by using the %<target%>"
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+ " attribute or pragma", "sme");
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+ }
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+}
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+
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/* This function is used by the call expanders of the machine description.
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RESULT is the register in which the result is returned. It's NULL for
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"call" and "sibcall".
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@@ -18194,6 +18211,19 @@ aarch64_override_options_internal (struct gcc_options *opts)
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&& !fixed_regs[R18_REGNUM])
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error ("%<-fsanitize=shadow-call-stack%> requires %<-ffixed-x18%>");
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+ if ((opts->x_aarch64_isa_flags & AARCH64_FL_SM_ON)
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+ && !(opts->x_aarch64_isa_flags & AARCH64_FL_SME))
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+ {
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+ error ("streaming functions require the ISA extension %qs", "sme");
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+ inform (input_location, "you can enable %qs using the command-line"
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+ " option %<-march%>, or by using the %<target%>"
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+ " attribute or pragma", "sme");
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+ opts->x_target_flags &= ~MASK_GENERAL_REGS_ONLY;
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+ auto new_flags = (opts->x_aarch64_asm_isa_flags
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+ | feature_deps::SME ().enable);
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+ aarch64_set_asm_isa_flags (opts, new_flags);
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+ }
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+
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initialize_aarch64_code_model (opts);
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initialize_aarch64_tls_size (opts);
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@@ -28159,6 +28189,9 @@ aarch64_get_v16qi_mode ()
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#undef TARGET_FUNCTION_VALUE_REGNO_P
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#define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
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+#undef TARGET_START_CALL_ARGS
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+#define TARGET_START_CALL_ARGS aarch64_start_call_args
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+
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#undef TARGET_GIMPLE_FOLD_BUILTIN
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#define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
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diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
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index 84215c8c3..dd2de4e88 100644
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--- a/gcc/config/aarch64/aarch64.h
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+++ b/gcc/config/aarch64/aarch64.h
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@@ -214,6 +214,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF;
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#define AARCH64_ISA_SVE2_BITPERM (aarch64_isa_flags & AARCH64_FL_SVE2_BITPERM)
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#define AARCH64_ISA_SVE2_SHA3 (aarch64_isa_flags & AARCH64_FL_SVE2_SHA3)
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#define AARCH64_ISA_SVE2_SM4 (aarch64_isa_flags & AARCH64_FL_SVE2_SM4)
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+#define AARCH64_ISA_SME (aarch64_isa_flags & AARCH64_FL_SME)
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#define AARCH64_ISA_V8_3A (aarch64_isa_flags & AARCH64_FL_V8_3A)
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#define AARCH64_ISA_DOTPROD (aarch64_isa_flags & AARCH64_FL_DOTPROD)
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#define AARCH64_ISA_AES (aarch64_isa_flags & AARCH64_FL_AES)
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@@ -292,6 +293,10 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF;
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/* SVE2 SM4 instructions, enabled through +sve2-sm4. */
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#define TARGET_SVE2_SM4 (AARCH64_ISA_SVE2_SM4)
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+/* SME instructions, enabled through +sme. Note that this does not
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+ imply anything about the state of PSTATE.SM. */
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+#define TARGET_SME (AARCH64_ISA_SME)
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+
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/* ARMv8.3-A features. */
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#define TARGET_ARMV8_3 (AARCH64_ISA_V8_3A)
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diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
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index 53709b246..2420b05d9 100644
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--- a/gcc/doc/invoke.texi
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+++ b/gcc/doc/invoke.texi
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@@ -19478,6 +19478,8 @@ Enable the instructions to accelerate memory operations like @code{memcpy},
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Enable the Flag Manipulation instructions Extension.
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@item pauth
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Enable the Pointer Authentication Extension.
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+@item sme
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+Enable the Scalable Matrix Extension.
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@end table
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diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
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index 454fae11a..80936a0eb 100644
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--- a/gcc/doc/sourcebuild.texi
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+++ b/gcc/doc/sourcebuild.texi
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@@ -2277,6 +2277,8 @@ AArch64 target which generates instruction sequences for big endian.
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@item aarch64_small_fpic
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Binutils installed on test system supports relocation types required by -fpic
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for AArch64 small memory model.
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+@item aarch64_sme
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+AArch64 target that generates instructions for SME.
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@item aarch64_sve_hw
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AArch64 target that is able to generate and execute SVE code (regardless of
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whether it does so by default).
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diff --git a/gcc/testsuite/g++.target/aarch64/sme/aarch64-sme.exp b/gcc/testsuite/g++.target/aarch64/sme/aarch64-sme.exp
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index 72fcd0bd9..1c3e69cde 100644
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--- a/gcc/testsuite/g++.target/aarch64/sme/aarch64-sme.exp
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+++ b/gcc/testsuite/g++.target/aarch64/sme/aarch64-sme.exp
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@@ -30,10 +30,16 @@ load_lib g++-dg.exp
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# Initialize `dg'.
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dg-init
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-aarch64-with-arch-dg-options "" {
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+if { [check_effective_target_aarch64_sme] } {
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+ set sme_flags ""
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+} else {
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+ set sme_flags "-march=armv9-a+sme"
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+}
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+
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+aarch64-with-arch-dg-options $sme_flags {
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# Main loop.
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dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
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- "" ""
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+ "" $sme_flags
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}
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# All done.
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diff --git a/gcc/testsuite/gcc.target/aarch64/sme/aarch64-sme.exp b/gcc/testsuite/gcc.target/aarch64/sme/aarch64-sme.exp
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index c990e5924..011310e80 100644
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--- a/gcc/testsuite/gcc.target/aarch64/sme/aarch64-sme.exp
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+++ b/gcc/testsuite/gcc.target/aarch64/sme/aarch64-sme.exp
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@@ -30,10 +30,16 @@ load_lib gcc-dg.exp
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# Initialize `dg'.
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dg-init
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-aarch64-with-arch-dg-options "" {
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+if { [check_effective_target_aarch64_sme] } {
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+ set sme_flags ""
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+} else {
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+ set sme_flags "-march=armv9-a+sme"
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+}
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+
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+aarch64-with-arch-dg-options $sme_flags {
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# Main loop.
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dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
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- "" ""
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+ "" $sme_flags
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}
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# All done.
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diff --git a/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_3.c b/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_3.c
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new file mode 100644
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index 000000000..45ec92321
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_3.c
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@@ -0,0 +1,63 @@
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+// { dg-options "" }
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+
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+#pragma GCC target "+nosme"
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+
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+void sc_a () [[arm::streaming_compatible]] {}
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+void s_a () [[arm::streaming]] {} // { dg-error "streaming functions require the ISA extension 'sme'" }
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+void ns_a () {}
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+
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+void sc_b () [[arm::streaming_compatible]] {}
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+void ns_b () {}
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+void s_b () [[arm::streaming]] {} // { dg-error "streaming functions require the ISA extension 'sme'" }
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+
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+void sc_c () [[arm::streaming_compatible]] {}
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+void sc_d () [[arm::streaming_compatible]] {}
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+
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+void s_c () [[arm::streaming]] {} // { dg-error "streaming functions require the ISA extension 'sme'" }
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+void s_d () [[arm::streaming]] {} // { dg-error "streaming functions require the ISA extension 'sme'" }
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+
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+void ns_c () {}
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+void ns_d () {}
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+
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+void sc_e () [[arm::streaming_compatible]];
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+void s_e () [[arm::streaming]];
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+void ns_e ();
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+
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+#pragma GCC target "+sme"
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+
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+void sc_f () [[arm::streaming_compatible]] {}
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+void s_f () [[arm::streaming]] {}
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+void ns_f () {}
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+
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+void sc_g () [[arm::streaming_compatible]] {}
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+void ns_g () {}
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+void s_g () [[arm::streaming]] {}
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+
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+void sc_h () [[arm::streaming_compatible]] {}
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+void sc_i () [[arm::streaming_compatible]] {}
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+
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+void s_h () [[arm::streaming]] {}
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+void s_i () [[arm::streaming]] {}
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+
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+void ns_h () {}
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+void ns_i () {}
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+
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+void sc_j () [[arm::streaming_compatible]];
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+void s_j () [[arm::streaming]];
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+void ns_j ();
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+
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+#pragma GCC target "+sme"
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+
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+void sc_k () [[arm::streaming_compatible]] {}
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+
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+#pragma GCC target "+nosme"
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+#pragma GCC target "+sme"
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+
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+void s_k () [[arm::streaming]] {}
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+
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+#pragma GCC target "+nosme"
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+#pragma GCC target "+sme"
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+
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+void ns_k () {}
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+
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+#pragma GCC target "+nosme"
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diff --git a/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_4.c b/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_4.c
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new file mode 100644
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index 000000000..50e92f2e1
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/aarch64/sme/streaming_mode_4.c
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@@ -0,0 +1,22 @@
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+// { dg-options "-mgeneral-regs-only" }
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+
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+void sc_a () [[arm::streaming_compatible]] {}
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+void s_a () [[arm::streaming]] {} // { dg-error "streaming functions require the ISA extension 'sme'" }
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+void ns_a () {}
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+
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+void sc_b () [[arm::streaming_compatible]] {}
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+void ns_b () {}
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+void s_b () [[arm::streaming]] {} // { dg-error "streaming functions require the ISA extension 'sme'" }
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+
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+void sc_c () [[arm::streaming_compatible]] {}
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+void sc_d () [[arm::streaming_compatible]] {}
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+
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+void s_c () [[arm::streaming]] {} // { dg-error "streaming functions require the ISA extension 'sme'" }
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+void s_d () [[arm::streaming]] {} // { dg-error "streaming functions require the ISA extension 'sme'" }
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+
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+void ns_c () {}
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+void ns_d () {}
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+
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+void sc_e () [[arm::streaming_compatible]];
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+void s_e () [[arm::streaming]];
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+void ns_e ();
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diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
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index bd89d4f52..e2a9ef5fa 100644
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--- a/gcc/testsuite/lib/target-supports.exp
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+++ b/gcc/testsuite/lib/target-supports.exp
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@@ -3887,6 +3887,18 @@ proc aarch64_sve_bits { } {
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}]
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}
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+# Return 1 if this is an AArch64 target that generates instructions for SME.
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+proc check_effective_target_aarch64_sme { } {
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+ if { ![istarget aarch64*-*-*] } {
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+ return 0
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+ }
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+ return [check_no_compiler_messages aarch64_sme assembly {
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+ #if !defined (__ARM_FEATURE_SME)
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+ #error FOO
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+ #endif
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+ }]
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+}
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+
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# Return 1 if this is a compiler supporting ARC atomic operations
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proc check_effective_target_arc_atomic { } {
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return [check_no_compiler_messages arc_atomic assembly {
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--
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2.33.0
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