254 lines
9.1 KiB
Diff
254 lines
9.1 KiB
Diff
From a2cc86c9b5e44c3dcdb8c52d6ae5f535442ec1d4 Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Sun, 17 Dec 2023 05:38:20 +0800
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Subject: [PATCH 088/188] LoongArch: Expand left rotate to right rotate with
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negated amount
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gcc/ChangeLog:
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* config/loongarch/loongarch.md (rotl<mode>3):
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New define_expand.
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* config/loongarch/simd.md (vrotl<mode>3): Likewise.
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(rotl<mode>3): Likewise.
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gcc/testsuite/ChangeLog:
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* gcc.target/loongarch/rotl-with-rotr.c: New test.
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* gcc.target/loongarch/rotl-with-vrotr-b.c: New test.
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* gcc.target/loongarch/rotl-with-vrotr-h.c: New test.
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* gcc.target/loongarch/rotl-with-vrotr-w.c: New test.
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* gcc.target/loongarch/rotl-with-vrotr-d.c: New test.
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* gcc.target/loongarch/rotl-with-xvrotr-b.c: New test.
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* gcc.target/loongarch/rotl-with-xvrotr-h.c: New test.
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* gcc.target/loongarch/rotl-with-xvrotr-w.c: New test.
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* gcc.target/loongarch/rotl-with-xvrotr-d.c: New test.
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---
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gcc/config/loongarch/loongarch.md | 12 ++++++++
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gcc/config/loongarch/simd.md | 29 +++++++++++++++++++
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.../gcc.target/loongarch/rotl-with-rotr.c | 9 ++++++
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.../gcc.target/loongarch/rotl-with-vrotr-b.c | 7 +++++
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.../gcc.target/loongarch/rotl-with-vrotr-d.c | 7 +++++
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.../gcc.target/loongarch/rotl-with-vrotr-h.c | 7 +++++
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.../gcc.target/loongarch/rotl-with-vrotr-w.c | 28 ++++++++++++++++++
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.../gcc.target/loongarch/rotl-with-xvrotr-b.c | 7 +++++
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.../gcc.target/loongarch/rotl-with-xvrotr-d.c | 7 +++++
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.../gcc.target/loongarch/rotl-with-xvrotr-h.c | 7 +++++
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.../gcc.target/loongarch/rotl-with-xvrotr-w.c | 7 +++++
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11 files changed, 127 insertions(+)
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create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-rotr.c
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create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-b.c
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create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-d.c
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create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-h.c
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create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-w.c
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create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-b.c
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create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-d.c
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create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-h.c
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create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-w.c
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diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
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index 3d5b75825..ed4d4b906 100644
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--- a/gcc/config/loongarch/loongarch.md
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+++ b/gcc/config/loongarch/loongarch.md
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@@ -2903,6 +2903,18 @@
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[(set_attr "type" "shift,shift")
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(set_attr "mode" "SI")])
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+;; Expand left rotate to right rotate.
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+(define_expand "rotl<mode>3"
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+ [(set (match_dup 3)
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+ (neg:SI (match_operand:SI 2 "register_operand")))
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+ (set (match_operand:GPR 0 "register_operand")
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+ (rotatert:GPR (match_operand:GPR 1 "register_operand")
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+ (match_dup 3)))]
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+ ""
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+ {
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+ operands[3] = gen_reg_rtx (SImode);
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+ });
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+
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;; The following templates were added to generate "bstrpick.d + alsl.d"
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;; instruction pairs.
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;; It is required that the values of const_immalsl_operand and
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diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md
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index 13202f79b..93fb39abc 100644
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--- a/gcc/config/loongarch/simd.md
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+++ b/gcc/config/loongarch/simd.md
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@@ -268,6 +268,35 @@
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[(set_attr "type" "simd_int_arith")
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(set_attr "mode" "<MODE>")])
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+;; Expand left rotate to right rotate.
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+(define_expand "vrotl<mode>3"
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+ [(set (match_dup 3)
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+ (neg:IVEC (match_operand:IVEC 2 "register_operand")))
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+ (set (match_operand:IVEC 0 "register_operand")
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+ (rotatert:IVEC (match_operand:IVEC 1 "register_operand")
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+ (match_dup 3)))]
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+ ""
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+ {
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+ operands[3] = gen_reg_rtx (<MODE>mode);
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+ });
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+
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+;; Expand left rotate with a scalar amount to right rotate: negate the
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+;; scalar before broadcasting it because scalar negation is cheaper than
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+;; vector negation.
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+(define_expand "rotl<mode>3"
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+ [(set (match_dup 3)
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+ (neg:SI (match_operand:SI 2 "register_operand")))
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+ (set (match_dup 4)
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+ (vec_duplicate:IVEC (subreg:<IVEC:UNITMODE> (match_dup 3) 0)))
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+ (set (match_operand:IVEC 0 "register_operand")
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+ (rotatert:IVEC (match_operand:IVEC 1 "register_operand")
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+ (match_dup 4)))]
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+ ""
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+ {
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+ operands[3] = gen_reg_rtx (SImode);
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+ operands[4] = gen_reg_rtx (<MODE>mode);
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+ });
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+
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;; <x>vrotri.{b/h/w/d}
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(define_insn "rotr<mode>3"
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diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-rotr.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-rotr.c
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new file mode 100644
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index 000000000..84cc53cec
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-rotr.c
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@@ -0,0 +1,9 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2" } */
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+/* { dg-final { scan-assembler "rotr\\.w" } } */
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+
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+unsigned
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+t (unsigned a, unsigned b)
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+{
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+ return a << b | a >> (32 - b);
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+}
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diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-b.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-b.c
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new file mode 100644
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index 000000000..14298bf9e
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-b.c
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@@ -0,0 +1,7 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mlsx -fno-vect-cost-model" } */
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+/* { dg-final { scan-assembler-times "vrotr\\.b" 2 } } */
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+/* { dg-final { scan-assembler-times "vneg\\.b" 1 } } */
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+
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+#define TYPE char
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+#include "rotl-with-vrotr-w.c"
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diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-d.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-d.c
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new file mode 100644
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index 000000000..0e971b323
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-d.c
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@@ -0,0 +1,7 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mlsx -fno-vect-cost-model" } */
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+/* { dg-final { scan-assembler-times "vrotr\\.d" 2 } } */
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+/* { dg-final { scan-assembler-times "vneg\\.d" 1 } } */
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+
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+#define TYPE long long
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+#include "rotl-with-vrotr-w.c"
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diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-h.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-h.c
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new file mode 100644
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index 000000000..93216ebc2
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-h.c
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@@ -0,0 +1,7 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mlsx -fno-vect-cost-model" } */
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+/* { dg-final { scan-assembler-times "vrotr\\.h" 2 } } */
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+/* { dg-final { scan-assembler-times "vneg\\.h" 1 } } */
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+
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+#define TYPE short
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+#include "rotl-with-vrotr-w.c"
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diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-w.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-w.c
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new file mode 100644
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index 000000000..d05b86f47
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr-w.c
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@@ -0,0 +1,28 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mlsx -fno-vect-cost-model" } */
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+/* { dg-final { scan-assembler-times "vrotr\\.w" 2 } } */
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+/* { dg-final { scan-assembler-times "vneg\\.w" 1 } } */
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+
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+#ifndef VLEN
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+#define VLEN 16
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+#endif
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+
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+#ifndef TYPE
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+#define TYPE int
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+#endif
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+
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+typedef unsigned TYPE V __attribute__ ((vector_size (VLEN)));
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+V a, b, c;
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+
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+void
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+test (int x)
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+{
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+ b = a << x | a >> ((int)sizeof (TYPE) * __CHAR_BIT__ - x);
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+}
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+
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+void
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+test2 (void)
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+{
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+ for (int i = 0; i < VLEN / sizeof (TYPE); i++)
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+ c[i] = a[i] << b[i] | a[i] >> ((int)sizeof (TYPE) * __CHAR_BIT__ - b[i]);
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+}
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diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-b.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-b.c
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new file mode 100644
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index 000000000..2674b1b61
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-b.c
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@@ -0,0 +1,7 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mlasx -fno-vect-cost-model" } */
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+/* { dg-final { scan-assembler-times "xvrotr\\.b" 2 } } */
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+/* { dg-final { scan-assembler-times "xvneg\\.b" 1 } } */
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+
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+#define VLEN 32
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+#include "rotl-with-vrotr-b.c"
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diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-d.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-d.c
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new file mode 100644
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index 000000000..e94403315
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-d.c
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@@ -0,0 +1,7 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mlasx -fno-vect-cost-model" } */
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+/* { dg-final { scan-assembler-times "xvrotr\\.d" 2 } } */
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+/* { dg-final { scan-assembler-times "xvneg\\.d" 1 } } */
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+
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+#define VLEN 32
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+#include "rotl-with-vrotr-d.c"
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diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-h.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-h.c
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new file mode 100644
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index 000000000..3d998941f
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-h.c
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@@ -0,0 +1,7 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mlasx -fno-vect-cost-model" } */
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+/* { dg-final { scan-assembler-times "xvrotr\\.h" 2 } } */
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+/* { dg-final { scan-assembler-times "xvneg\\.h" 1 } } */
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+
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+#define VLEN 32
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+#include "rotl-with-vrotr-h.c"
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diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-w.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-w.c
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new file mode 100644
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index 000000000..ca6aa7bae
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr-w.c
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@@ -0,0 +1,7 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mlasx -fno-vect-cost-model" } */
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+/* { dg-final { scan-assembler-times "xvrotr\\.w" 2 } } */
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+/* { dg-final { scan-assembler-times "xvneg\\.w" 1 } } */
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+
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+#define VLEN 32
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+#include "rotl-with-vrotr-w.c"
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--
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2.43.0
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