62 lines
2.1 KiB
Diff
62 lines
2.1 KiB
Diff
From 42368d6ab1200c157ff473c37889b56b596040e2 Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Thu, 16 Nov 2023 09:30:14 +0800
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Subject: [PATCH 038/188] LoongArch: Don't emit dbar 0x700 if -mld-seq-sa
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This option (CPUCFG word 0x3 bit 23) means "the hardware guarantee that
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two loads on the same address won't be reordered with each other". Thus
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we can omit the "load-load" barrier dbar 0x700.
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This is only a micro-optimization because dbar 0x700 is already treated
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as nop if the hardware supports LD_SEQ_SA.
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gcc/ChangeLog:
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* config/loongarch/loongarch.cc (loongarch_print_operand): Don't
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print dbar 0x700 if TARGET_LD_SEQ_SA.
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* config/loongarch/sync.md (atomic_load<mode>): Likewise.
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---
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gcc/config/loongarch/loongarch.cc | 2 +-
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gcc/config/loongarch/sync.md | 9 +++++----
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2 files changed, 6 insertions(+), 5 deletions(-)
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diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
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index 8bd46da62..c86b787c4 100644
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--- a/gcc/config/loongarch/loongarch.cc
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+++ b/gcc/config/loongarch/loongarch.cc
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@@ -6057,7 +6057,7 @@ loongarch_print_operand (FILE *file, rtx op, int letter)
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if (loongarch_cas_failure_memorder_needs_acquire (
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memmodel_from_int (INTVAL (op))))
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fputs ("dbar\t0b10100", file);
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- else
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+ else if (!TARGET_LD_SEQ_SA)
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fputs ("dbar\t0x700", file);
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break;
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diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md
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index f4673c856..65443c899 100644
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--- a/gcc/config/loongarch/sync.md
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+++ b/gcc/config/loongarch/sync.md
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@@ -119,13 +119,14 @@
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case MEMMODEL_SEQ_CST:
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return "dbar\t0x11\\n\\t"
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"ld.<size>\t%0,%1\\n\\t"
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- "dbar\t0x14\\n\\t";
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+ "dbar\t0x14";
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case MEMMODEL_ACQUIRE:
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return "ld.<size>\t%0,%1\\n\\t"
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- "dbar\t0x14\\n\\t";
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+ "dbar\t0x14";
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case MEMMODEL_RELAXED:
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- return "ld.<size>\t%0,%1\\n\\t"
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- "dbar\t0x700\\n\\t";
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+ return TARGET_LD_SEQ_SA ? "ld.<size>\t%0,%1\\n\\t"
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+ : "ld.<size>\t%0,%1\\n\\t"
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+ "dbar\t0x700";
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default:
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/* The valid memory order variants are __ATOMIC_RELAXED, __ATOMIC_SEQ_CST,
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--
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2.43.0
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