117 lines
3.7 KiB
Diff
117 lines
3.7 KiB
Diff
From b8f47a362000bb51dec88e0a73f885c57a46f568 Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Sun, 12 Nov 2023 00:55:13 +0800
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Subject: [PATCH 024/188] LoongArch: Use simplify_gen_subreg instead of
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gen_rtx_SUBREG in loongarch_expand_vec_cond_mask_expr [PR112476]
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GCC internal says:
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'subreg's of 'subreg's are not supported. Using
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'simplify_gen_subreg' is the recommended way to avoid this problem.
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Unfortunately loongarch_expand_vec_cond_mask_expr might create nested
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subreg under certain circumstances, causing an ICE.
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Use simplify_gen_subreg as the internal document suggests.
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gcc/ChangeLog:
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PR target/112476
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* config/loongarch/loongarch.cc
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(loongarch_expand_vec_cond_mask_expr): Call simplify_gen_subreg
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instead of gen_rtx_SUBREG.
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gcc/testsuite/ChangeLog:
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PR target/112476
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* gcc.target/loongarch/pr112476-1.c: New test.
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* gcc.target/loongarch/pr112476-2.c: New test.
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---
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gcc/config/loongarch/loongarch.cc | 11 ++++++---
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.../gcc.target/loongarch/pr112476-1.c | 24 +++++++++++++++++++
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.../gcc.target/loongarch/pr112476-2.c | 5 ++++
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3 files changed, 37 insertions(+), 3 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/loongarch/pr112476-1.c
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create mode 100644 gcc/testsuite/gcc.target/loongarch/pr112476-2.c
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diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
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index fa5c14be6..65ca1489f 100644
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--- a/gcc/config/loongarch/loongarch.cc
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+++ b/gcc/config/loongarch/loongarch.cc
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@@ -11190,7 +11190,9 @@ loongarch_expand_vec_cond_mask_expr (machine_mode mode, machine_mode vimode,
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if (mode != vimode)
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{
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xop1 = gen_reg_rtx (vimode);
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- emit_move_insn (xop1, gen_rtx_SUBREG (vimode, operands[1], 0));
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+ emit_move_insn (xop1,
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+ simplify_gen_subreg (vimode, operands[1],
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+ mode, 0));
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}
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emit_move_insn (src1, xop1);
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}
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@@ -11207,7 +11209,9 @@ loongarch_expand_vec_cond_mask_expr (machine_mode mode, machine_mode vimode,
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if (mode != vimode)
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{
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xop2 = gen_reg_rtx (vimode);
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- emit_move_insn (xop2, gen_rtx_SUBREG (vimode, operands[2], 0));
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+ emit_move_insn (xop2,
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+ simplify_gen_subreg (vimode, operands[2],
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+ mode, 0));
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}
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emit_move_insn (src2, xop2);
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}
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@@ -11226,7 +11230,8 @@ loongarch_expand_vec_cond_mask_expr (machine_mode mode, machine_mode vimode,
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gen_rtx_AND (vimode, mask, src1));
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/* The result is placed back to a register with the mask. */
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emit_insn (gen_rtx_SET (mask, bsel));
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- emit_move_insn (operands[0], gen_rtx_SUBREG (mode, mask, 0));
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+ emit_move_insn (operands[0], simplify_gen_subreg (mode, mask,
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+ vimode, 0));
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}
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}
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diff --git a/gcc/testsuite/gcc.target/loongarch/pr112476-1.c b/gcc/testsuite/gcc.target/loongarch/pr112476-1.c
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new file mode 100644
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index 000000000..4cf133e7a
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/pr112476-1.c
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@@ -0,0 +1,24 @@
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+/* PR target/112476: ICE with -mlsx */
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -march=loongarch64 -mfpu=64 -mabi=lp64d -mlsx" } */
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+
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+int foo, bar;
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+float baz, res, a;
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+
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+void
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+apply_adjacent_ternary (float *dst, float *src0)
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+{
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+ do
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+ {
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+ __builtin_memcpy (&res, &src0, sizeof (res));
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+ *dst = foo ? baz : res;
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+ dst++;
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+ }
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+ while (dst != src0);
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+}
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+
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+void
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+xx (void)
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+{
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+ apply_adjacent_ternary (&a, &a);
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+}
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diff --git a/gcc/testsuite/gcc.target/loongarch/pr112476-2.c b/gcc/testsuite/gcc.target/loongarch/pr112476-2.c
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new file mode 100644
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index 000000000..cc0dfbfc9
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/pr112476-2.c
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@@ -0,0 +1,5 @@
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+/* PR target/112476: ICE with -mlasx */
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -march=loongarch64 -mfpu=64 -mabi=lp64d -mlasx" } */
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+
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+#include "pr112476-1.c"
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--
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2.43.0
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