51 lines
1.6 KiB
Diff
51 lines
1.6 KiB
Diff
From d10807504a7f4e58a7dd1fa245d0ccf16227d222 Mon Sep 17 00:00:00 2001
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From: Chernonog Viacheslav <chernonog.vyacheslav@huawei.com>
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Date: Wed, 4 Dec 2024 20:07:23 +0800
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Subject: [PATCH] [Bugfix] replace tmp pattern split
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move split before reload
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change split tmp pattern to 3 instructions
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---
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gcc/config/aarch64/aarch64-simd.md | 19 +++++++++++++------
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1 file changed, 13 insertions(+), 6 deletions(-)
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diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
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index 04592fc90..fb5e355d0 100644
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--- a/gcc/config/aarch64/aarch64-simd.md
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+++ b/gcc/config/aarch64/aarch64-simd.md
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@@ -6566,18 +6566,25 @@
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(match_operand:VDQHSD 1 "register_operand" "w")
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(match_operand:VDQHSD 2 "half_size_minus_one_operand"))
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(match_operand:VDQHSD 3 "cmlt_arith_mask_operand")))]
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- "TARGET_SIMD && flag_cmlt_arith"
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+ "TARGET_SIMD && !reload_completed && flag_cmlt_arith"
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"#"
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- "&& reload_completed"
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- [(set (match_operand:<V_INT_EQUIV> 0 "register_operand")
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+ "&& true"
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+ [(set (match_operand:<V_INT_EQUIV> 0 "register_operand" "=w")
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(lshiftrt:<V_INT_EQUIV>
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(match_operand:VDQHSD 1 "register_operand")
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(match_operand:VDQHSD 2 "half_size_minus_one_operand")))
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+ (set (match_operand:<V_INT_EQUIV> 4 "register_operand" "w")
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+ (match_operand:VDQHSD 3 "cmlt_arith_mask_operand"))
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(set (match_dup 0)
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(and:<V_INT_EQUIV>
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- (match_dup 0)
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- (match_operand:VDQHSD 3 "cmlt_arith_mask_operand")))]
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- ""
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+ (match_dup 4)
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+ (match_dup 0)))]
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+ {
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+ if (can_create_pseudo_p ())
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+ operands[4] = gen_reg_rtx (<V_INT_EQUIV>mode);
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+ else
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+ FAIL;
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+ }
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[(set_attr "type" "neon_compare_zero")]
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)
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--
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2.33.0
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