157 lines
5.1 KiB
Diff
157 lines
5.1 KiB
Diff
From 6b483504c4fbb2a05a17d67e8f51b72149f1bbf9 Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Thu, 16 Nov 2023 09:21:47 +0800
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Subject: [PATCH 037/188] LoongArch: Take the advantage of -mdiv32 if it's
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enabled
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With -mdiv32, we can assume div.w[u] and mod.w[u] works on low 32 bits
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of a 64-bit GPR even if it's not sign-extended.
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gcc/ChangeLog:
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* config/loongarch/loongarch.md (DIV): New mode iterator.
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(<optab:ANY_DIV><mode:GPR>3): Don't expand if TARGET_DIV32.
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(<optab:ANY_DIV>di3_fake): Disable if TARGET_DIV32.
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(*<optab:ANY_DIV><mode:GPR>3): Allow SImode if TARGET_DIV32.
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(<optab:ANY_DIV>si3_extended): New insn if TARGET_DIV32.
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gcc/testsuite/ChangeLog:
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* gcc.target/loongarch/div-div32.c: New test.
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* gcc.target/loongarch/div-no-div32.c: New test.
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---
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gcc/config/loongarch/loongarch.md | 31 ++++++++++++++++---
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.../gcc.target/loongarch/div-div32.c | 31 +++++++++++++++++++
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.../gcc.target/loongarch/div-no-div32.c | 11 +++++++
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3 files changed, 68 insertions(+), 5 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/loongarch/div-div32.c
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create mode 100644 gcc/testsuite/gcc.target/loongarch/div-no-div32.c
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diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
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index 52e40a208..c4e7af107 100644
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--- a/gcc/config/loongarch/loongarch.md
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+++ b/gcc/config/loongarch/loongarch.md
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@@ -408,6 +408,10 @@
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;; st.w.
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(define_mode_iterator ST_ANY [QHWD ANYF])
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+;; A mode for anything legal as a input of a div or mod instruction.
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+(define_mode_iterator DIV [(DI "TARGET_64BIT")
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+ (SI "!TARGET_64BIT || TARGET_DIV32")])
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+
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;; In GPR templates, a string like "mul.<d>" will expand to "mul.w" in the
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;; 32-bit version and "mul.d" in the 64-bit version.
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(define_mode_attr d [(SI "w") (DI "d")])
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@@ -914,7 +918,7 @@
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(match_operand:GPR 2 "register_operand")))]
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""
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{
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- if (GET_MODE (operands[0]) == SImode && TARGET_64BIT)
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+ if (GET_MODE (operands[0]) == SImode && TARGET_64BIT && !TARGET_DIV32)
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{
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rtx reg1 = gen_reg_rtx (DImode);
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rtx reg2 = gen_reg_rtx (DImode);
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@@ -934,9 +938,9 @@
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})
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(define_insn "*<optab><mode>3"
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- [(set (match_operand:X 0 "register_operand" "=r,&r,&r")
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- (any_div:X (match_operand:X 1 "register_operand" "r,r,0")
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- (match_operand:X 2 "register_operand" "r,r,r")))]
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+ [(set (match_operand:DIV 0 "register_operand" "=r,&r,&r")
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+ (any_div:DIV (match_operand:DIV 1 "register_operand" "r,r,0")
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+ (match_operand:DIV 2 "register_operand" "r,r,r")))]
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""
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{
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return loongarch_output_division ("<insn>.<d><u>\t%0,%1,%2", operands);
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@@ -949,6 +953,23 @@
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(const_string "yes")
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(const_string "no")))])
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+(define_insn "<optab>si3_extended"
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+ [(set (match_operand:DI 0 "register_operand" "=r,&r,&r")
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+ (sign_extend
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+ (any_div:SI (match_operand:SI 1 "register_operand" "r,r,0")
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+ (match_operand:SI 2 "register_operand" "r,r,r"))))]
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+ "TARGET_64BIT && TARGET_DIV32"
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+{
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+ return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands);
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+}
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+ [(set_attr "type" "idiv")
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+ (set_attr "mode" "SI")
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+ (set (attr "enabled")
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+ (if_then_else
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+ (match_test "!!which_alternative == loongarch_check_zero_div_p()")
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+ (const_string "yes")
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+ (const_string "no")))])
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+
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(define_insn "<optab>di3_fake"
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[(set (match_operand:DI 0 "register_operand" "=r,&r,&r")
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(sign_extend:DI
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@@ -957,7 +978,7 @@
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(any_div:DI (match_operand:DI 1 "register_operand" "r,r,0")
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(match_operand:DI 2 "register_operand" "r,r,r")) 0)]
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UNSPEC_FAKE_ANY_DIV)))]
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- "TARGET_64BIT"
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+ "TARGET_64BIT && !TARGET_DIV32"
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{
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return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands);
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}
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diff --git a/gcc/testsuite/gcc.target/loongarch/div-div32.c b/gcc/testsuite/gcc.target/loongarch/div-div32.c
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new file mode 100644
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index 000000000..8b1f686ec
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/div-div32.c
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@@ -0,0 +1,31 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -mdiv32" } */
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+/* { dg-final { scan-assembler "div\.w" } } */
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+/* { dg-final { scan-assembler "div\.wu" } } */
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+/* { dg-final { scan-assembler "mod\.w" } } */
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+/* { dg-final { scan-assembler "mod\.wu" } } */
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+/* { dg-final { scan-assembler-not "slli\.w.*,0" } } */
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+
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+int
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+divw (long a, long b)
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+{
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+ return (int)a / (int)b;
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+}
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+
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+unsigned int
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+divwu (long a, long b)
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+{
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+ return (unsigned int)a / (unsigned int)b;
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+}
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+
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+int
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+modw (long a, long b)
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+{
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+ return (int)a % (int)b;
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+}
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+
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+unsigned int
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+modwu (long a, long b)
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+{
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+ return (unsigned int)a % (unsigned int)b;
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+}
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diff --git a/gcc/testsuite/gcc.target/loongarch/div-no-div32.c b/gcc/testsuite/gcc.target/loongarch/div-no-div32.c
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new file mode 100644
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index 000000000..f0f697ba5
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/div-no-div32.c
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@@ -0,0 +1,11 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */
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+/* { dg-final { scan-assembler "div\.w" } } */
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+/* { dg-final { scan-assembler "div\.wu" } } */
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+/* { dg-final { scan-assembler "mod\.w" } } */
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+/* { dg-final { scan-assembler "mod\.wu" } } */
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+
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+/* -mno-div32 should be implied by -march=loongarch64. */
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+/* { dg-final { scan-assembler-times "slli\.w\[^\n\]*0" 8 } } */
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+
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+#include "div-div32.c"
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--
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2.43.0
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