a1e8d45430
The HCCS and SDMA modules and the log collection function are added. Signed-off-by: zhangyuyang <zhangyuyang31@huawei.com> (cherry picked from commit 73fe961568c3b5e4406a65a46e926f2f0623d585)
60 lines
2.0 KiB
Diff
60 lines
2.0 KiB
Diff
From 4fa7bfb97799f85940d2c8cec1a2078a3a637d4d Mon Sep 17 00:00:00 2001
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From: moubingquan <moubingquan@huawei.com>
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Date: Fri, 20 Dec 2024 15:03:30 +0800
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Subject: [PATCH 69/81] [hikptool/ pcie]:The query result of pcie_dumpreg does
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not match the register list.
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Rectify the problem that the pcie_regdump
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command dump registers do not match the register table.
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Signed-off-by: moubingquan <moubingquan@huawei.com>
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---
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pcie/func_lib/pcie_func/pcie_reg_dump.c | 8 ++------
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1 file changed, 2 insertions(+), 6 deletions(-)
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diff --git a/pcie/func_lib/pcie_func/pcie_reg_dump.c b/pcie/func_lib/pcie_func/pcie_reg_dump.c
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index 4172637..ad7cc7f 100644
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--- a/pcie/func_lib/pcie_func/pcie_reg_dump.c
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+++ b/pcie/func_lib/pcie_func/pcie_reg_dump.c
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@@ -64,10 +64,8 @@ struct pcie_dumpreg_info g_reg_table_tl[] = {
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{0, "TL_RX_NONPOST_CNT"},
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{0, "TL_RX_CPL_CNT"},
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{0, "TL_RX_LOC_TLP_CNT"},
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- {0, "TL_RX_ERR_STATUS"},
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{0, "TL_CFGSPACE_BDF"},
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{0, "TL_TX_UR_CNT"},
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- {0, "TL_RX_ERR_STATUS"},
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};
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struct pcie_dumpreg_info g_reg_table_dl[] = {
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@@ -126,7 +124,6 @@ struct pcie_dumpreg_info g_reg_table_mac[] = {
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{0, "MAC_REG_DEBUG_PIPE9"},
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{0, "MAC_REG_DEBUG_PIPE10"},
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{0, "MAC_REG_DEBUG_PIPE11"},
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- {0, "MAC_LEAVE_L0_INFO"},
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{0, "DFX_APB_LANE_ERROR_STATUS_0"},
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{0, "DFX_APB_LANE_ERROR_STATUS_1"},
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{0, "MAC_REG_PHY_RXDATA_TS_REG"},
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@@ -255,7 +252,6 @@ struct pcie_dumpreg_info g_reg_table_iob_rx[] = {
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{0, "DFX_IOB_RX_CNT_RESP_RX"},
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{0, "DFX_IOB_RX_CNT_RESP_LOC"},
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{0, "DFX_IOB_RX_CNT_RESP_RECV"},
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- {0, "IOB_RX_INT_STATUS"},
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{0, "DFX_IOB_RX_AMB_WR_CNT_0"},
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{0, "DFX_IOB_RX_AMB_WR_CNT_1"},
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{0, "DFX_IOB_RX_AMB_RD_CNT_0"},
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@@ -369,8 +365,8 @@ struct pcie_dumpreg_info g_reg_table_core_glb[] = {
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{0, "CORE_INT_FE_RO_2"},
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{0, "PORT07_LINK_MODE"},
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{0, "PORT815_LINK_MODE"},
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- {0, "PCIE_LINK_DOWN_CLR_PORT_EN_REG"},
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- {0, "CORE_CLK_FLG_REG"},
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+ {0, "PCIE_LINK_DOWN_CLR_PORT_EN"},
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+ {0, "CORE_CLK_FLG"},
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};
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struct pcie_dumpreg_info g_reg_table_core_tl[] = {
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--
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2.45.0.windows.1
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