python-watchfiles/0002-backport-from-target-lexicon-0.12.7.patch
2024-10-16 10:47:28 +08:00

65 lines
2.2 KiB
Diff

From a40ade7076fae3e2a1b979bde952ded2d02dee86 Mon Sep 17 00:00:00 2001
From: Wenlong Zhang <zhangwenlong@loongson.cn>
Date: Wed, 16 Oct 2024 10:35:23 +0800
Subject: [PATCH 1/2] backport from target lexicon 0.12.7
---
vendor/target-lexicon/src/targets.rs | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/vendor/target-lexicon/src/targets.rs b/vendor/target-lexicon/src/targets.rs
index 9fe4d79..5ae0e08 100644
--- a/vendor/target-lexicon/src/targets.rs
+++ b/vendor/target-lexicon/src/targets.rs
@@ -24,6 +24,7 @@ pub enum Architecture {
Hexagon,
X86_32(X86_32Architecture),
M68k,
+ LoongArch64,
Mips32(Mips32Architecture),
Mips64(Mips64Architecture),
Msp430,
@@ -550,6 +551,7 @@ impl Architecture {
| Bpfel
| Hexagon
| X86_32(_)
+ | LoongArch64
| Mips64(Mips64Architecture::Mips64el)
| Mips32(Mips32Architecture::Mipsel)
| Mips32(Mips32Architecture::Mipsisa32r6el)
@@ -612,6 +614,7 @@ impl Architecture {
| S390x
| Sparc64
| Sparcv9
+ | LoongArch64
| Wasm64
| Clever(_) => Ok(PointerWidth::U64),
}
@@ -805,6 +808,7 @@ impl fmt::Display for Architecture {
Bpfel => f.write_str("bpfel"),
Hexagon => f.write_str("hexagon"),
X86_32(x86_32) => x86_32.fmt(f),
+ LoongArch64 => f.write_str("loongarch64"),
M68k => f.write_str("m68k"),
Mips32(mips32) => mips32.fmt(f),
Mips64(mips64) => mips64.fmt(f),
@@ -1002,6 +1006,7 @@ impl FromStr for Architecture {
"bpfeb" => Bpfeb,
"bpfel" => Bpfel,
"hexagon" => Hexagon,
+ "loongarch64" => LoongArch64,
"m68k" => M68k,
"msp430" => Msp430,
"nvptx64" => Nvptx64,
@@ -1484,6 +1489,7 @@ mod tests {
"i686-uwp-windows-gnu",
"i686-uwp-windows-msvc",
"i686-wrs-vxworks",
+ "loongarch64-unknown-linux-gnu",
"m68k-unknown-linux-gnu",
"mips64el-unknown-linux-gnuabi64",
"mips64el-unknown-linux-muslabi64",
--
2.43.0